tag: Stanford University

Chip Industry Technical Paper Roundup: Sept. 1
By Linda Christensen - 01 Sep, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation Georgia Tech ROBBIN: Rowhammer-Based Backdoor Injection during Inference Northeastern University An Open-Sourc... » read more

Programmable Silicon Photonics Filter Enables Continuous Laser Wavelength Tuning (UiT, Stanford)
By Technical Paper Link - 30 Aug, 2026 - Comments: 0

Researchers at UiT The Arctic University of Norway and Stanford University published a technical paper titled “Intracavity Laser Wavelength Tuning by a Programmable Forward-Only Silicon Photonics Interferometer Mesh.” Abstract Excerpt: “We exploit a recently proposed concept for a programmable, mechanically robust, and tunable nonresonant silicon photonic integrated circuit filte... » read more

Deep Learning Automates Parameter Extraction For 2D Transistors (Stanford, SLAC)
By Technical Paper Link - 28 Aug, 2026 - Comments: 0

Researchers from Stanford University and SLAC National Accelerator Laboratory published a technical paper titled “Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors.” Abstract Excerpt: "We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, and defect profiles) of two-dimensional (2... » read more

Ultrafast X-Ray Diffraction Maps Thermal Transport In GaN Thin Films (MIT, SLAC, Stanford, Argonne)
By Technical Paper Link - 07 Aug, 2026 - Comments: 0

Researchers from MIT, SLAC, Stanford University, and Argonne National Laboratory published a technical paper titled “Spatiotemporal mapping of anisotropic thermal transport in GaN thin films via ultrafast X-ray diffraction.” Abstract Excerpt: The paper presents a “non-contact, spatiotemporal-resolved ultrafast X-ray diffraction method to extract in-plane thermal conductivity and therma... » read more

Chip Industry Technical Paper Roundup: Aug. 4
By Linda Christensen - 04 Aug, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations The SpiNNaker2 Chip: A Many-Core Platform for Flexible and Scalable Brain-Inspired Computing 🔗 TU Dresden, University of Manchester Granite: A Modular Methodology for Foundational Verification of Hardware-Software Leakage Contracts 🔗... » read more

2D P-Type Semiconductors with Oxide N-Channel Transistors For Complementary BEOL CMOS (Stanford, Hanyang)
By Technical Paper Link - 29 Jul, 2026 - Comments: 0

Researchers from Stanford University and Hanyang University published a technical paper titled “Bridging the p-type gap in oxide electronics with 2D semiconductors.” "The review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle p-doping, and mitigation of crystallizatio... » read more

Research Bits: July 21
By Jesse Allen - 21 Jul, 2026 - Comments: 0

Thin TMD transistors Researchers from Chalmers University of Technology and Stanford University fabricated transistors from three different atomically thin 2D semiconductors with channel widths as small as 25nm. “These are some of the slimmest high-performance transistors demonstrated in two-dimensional semiconductors,” said Anton Persson, assistant professor at Chalmers University of T... » read more

Research Bits: June 30
By Jesse Allen - 30 Jun, 2026 - Comments: 0

Monolithic 3D integration Researchers from the University of Illinois Urbana-Champaign developed a low-temperature process for monolithic 3D integration using standard single-crystalline silicon. “Generally, the industry accepts that once the first layer of circuits is complete, the thermal budget limit for any additional layers is 400 degrees Celsius,” said Qing Cao, a materials scienc... » read more

Research Bits: June 15
By Jesse Allen - 15 Jun, 2026 - Comments: 0

NAND in space Researchers from Georgia Institute of Technology and Pennsylvania State University built ferroelectric NAND flash memory chips that can withstand up to 30 times higher radiation levels compared to conventional NAND. “If you send traditional flash memory to space, the radiation interacting with flash memory’s trapped electric charge can easily corrupt the data,” said Asif... » read more

Chip Industry Technical Paper Roundup: June 8
By Linda Christensen - 08 Jun, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 🔗 imec, KU Leuven ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs 🔗 KAIST Thermal- and Aging-Aware Rowhamme... » read more

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