tag: reliability

AI Agent Orchestration For ASIC Autonomy
By Ed Sperling - 27 Jul, 2026 - Comments: 0

The use of AI agents in chip design has been limited to small portions of the design flow. Engineers have been proceeding cautiously to understand how agents work, how to ensure they are delivering consistent results, and how different agents work together. The next step is to extend their role beyond just gluing together coding and tooling functions. Mehir Arora, head of engineering at ChipAge... » read more

Using Reliability Degradation Parameters To Drive Better Design Choices
By Niyati Singh - 23 Jul, 2026 - Comments: 0

A circuit can look perfect on day one and still drift out of specification after months or years of electrical and thermal stress. That is the reliability problem in a nutshell: the design does not only need to work when devices are fresh; the design must continue to meet performance expectations as devices age. A useful real-life analogy is a new car engine. A day-one test tells whether the... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test
By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Moving Defect Detection And Classification To The Edge
By Ed Sperling - 29 May, 2026 - Comments: 0

The number of defects detected through inspection is exploding at each new process node. There are now millions of defects being identified on each wafer, but only a fraction of those can cause problems. Prasad Bachiraju, senior director of business development at Onto Innovation, talks about the different types of images being captured using different illumination modes at different touch poin... » read more

Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)
By Technical Paper Link - 25 May, 2026 - Comments: 0

A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

When Semiconductor Materials Misbehave
By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

System-in-Package Challenges
By Ed Sperling - 23 Apr, 2026 - Comments: 0

Systems companies and leading-edge chipmakers are pushing past reticle limits with chiplet-based designs, often breaking compute-intensive functions into different chiplets and coupling those with other chiplets that may have been developed by different teams and at different process nodes. This is harder than it sounds, and results can vary widely even under the best circumstances. Nir Sever, ... » read more

Silent Data Corruption: A Major Reliability Challenge in Large-Scale LLM Training (TU Berlin)
By Technical Paper Link - 12 Apr, 2026 - Comments: 0

A new technical paper, "Exploring Silent Data Corruption as a Reliability Challenge in LLM Training," was published by researchers at Technische Universitat Berlin. Abstract "As Large Language Models (LLMs) scale in size and complexity, the consequences of failures during training become increasingly severe. A major challenge arises from Silent Data Corruption (SDC): hardware-induced faults... » read more

Enhancing Silicon Reliability With In-System Test And SLM Data
By Adam Cron - 07 Apr, 2026 - Comments: 0

Innovation in semiconductor development and manufacturing shows no signs of slowing down. Ever-larger chips at ever-smaller geometries create new challenges all the time. At the same time, competitive pressures are shrinking time to market (TTM) and putting enormous pressure on project teams. Furthermore, the wide use of electronics in safety-critical applications demands better reliability, av... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

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