Chip Industry Week in Review


Memory/FMS Denser, faster, and more distributed memory architectures for AI was the big news at the Future of Memory and Storage conference this week: Sandisk and SK hynix released the High Bandwidth Flash (HBF) spec, outlining basic performance expectations, the xPU-HBF host interface, and reliability and packaging guidance for an HBF die stack. Samsung showed concept models of zHBM... » read more

Chip Industry Week In Review


DAC: Chips to Systems Conference  The energy and buzz at this year's Design Automation Conference surprised everyone — despite initial concerns about its location in Long Beach, California, which is well off the beaten path for semiconductors. Hot topics included AI automation, multiphysics simulation, compute-in-memory, chiplets, physical  AI, and the development and orchestration of AI a... » read more

Chip Industry Week In Review


Notable deals  Amkor and Nvidia signed a $1.5B multiyear agreement to develop advanced packaging and test technologies for next-gen AI and accelerated-computing platforms. Nvidia’s prepayment will support Amkor’s U.S. capacity expansion in Arizona, including high-density interconnect and heterogeneous integration capabilities. Siemens announced plans to acquire two EDA companies: D... » read more

Chip Industry Week In Review


Around the world South Korea unveiled a sweeping AI and semiconductor investment drive, planning three mega projects that tie semiconductors, physical AI/robotics, and AI data centers into a single industrial plan, with government support for regional chip clusters, packaging capacity, power, water, sites, and workforce development. Among the new investments: Samsung will spend $260B on n... » read more

Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

AI Growing Impact On Chip Design And EDA Tools


Key Takeaways Many workflows in the data center are customer-specific, which is part of the reason there is so much interest in agentic AI-enabled tools. Large systems companies are pressing EDA vendors for performance improvements to keep pace with their AI workflows. The makeup of design teams is changing as AI infiltrates more of the chip design process. Experts at the Ta... » read more

DRAM’s Whac‑A‑Mole Security Crisis


Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

AI’s Potential And Limitations In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

Chip Industry Technical Paper Roundup: Mar. 31


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips 🔗 ETH Zurich, Rutgers University Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review 🔗 Univ... » read more

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