tag: hardware security

The Next Big Chip Failure May Be A Security One
By Ann Mutschler - 06 Aug, 2026 - Comments: 0

Key Takeaways:  Chip security must be designed in from the start, with clear requirements that connect architecture, verification, software, manufacturing, and field deployment. AI is expanding both the scale and accessibility of attacks, making hardware-level vulnerabilities harder to anticipate, patch, and contain. Regulations, customer expectations, and lifecycle risks are turnin... » read more

Embedded HSM Root of Trust with Arm Cortex-M33 Processor
By Rambus - 05 Aug, 2026 - Comments: 0

The Rambus CryptoManager RT-648 Root of Trust is a fully-programmable hardware security core offering security by design for automotive applications. As the connected nature of automobiles evolves, device architects face a growing array of emerging security threats. Whether V2X, ADAS, infotainment, or other applications, one constant is the need for a hardware Root of Trust-based security imple... » read more

A Selective Magneto‐ionic Strategy for Hardware‐level Security
By Technical Paper Link - 04 Aug, 2026 - Comments: 0

Researchers from Universitat Autònoma de Barcelona, INRiM, ICN2 and ICREA published a technical paper titled “Voltage-Reconfigurable Magneto-Ionic Nanolayers in Dot Arrays for Probabilistic, Materials-Engineered Security Primitives.” The paper explores "a selective magneto‐ionic strategy for hardware‐level security that exploits voltage‐controlled N3- ion migration within pre‐de... » read more

Modular Verification of RTL Processors Against ISA Contracts (MIT, Google, UW)
By Technical Paper Link - 02 Aug, 2026 - Comments: 0

Researchers from MIT, Google, and University of Washington published a technical paper titled “Granite: A Modular Methodology for Foundational Verification of Hardware-Software Leakage Contracts.” Abstract Excerpt: "Granite is a methodology for modular verification of both functional correctness and nonleakage of RTL processors against ISA contracts. We prove that the cycle-by-cycle timi... » read more

Pre-Silicon Power Side-Channel Leakage In Processors (University of Lübeck)
By Technical Paper Link - 28 Jul, 2026 - Comments: 0

Researchers from University of Lübeck published a technical paper titled “SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.” Abstract Excerpt: “This paper presents SPARC, an automated framework for pre-silicon PSCL evaluation and root-cause analysis. SPARC leverages macro-cell-level Information Flow Tracking (IFT) augmented wi... » read more

Enabling Comprehensive CWE-based Assurance for RISC-V Processors
By Arteris - 22 Jul, 2026 - Comments: 0

Abstract This paper presents a scalable, Common Weakness Enumeration (CWE)–based security assurance methodology for third-party RISC-V processor IP, developed collaboratively by Cycuity, BAE Systems, and SiFive. The approach adapts the MITRE Corporation CWE framework to systematically derive security requirements, verification properties, and evidence for RISC-V cores treated as third-party ... » read more

Build Your Device Security Test Lab
By Keysight - 01 Jul, 2026 - Comments: 0

Embedded systems are becoming more powerful, more connected, and more exposed. At the same time, attacks on hardware evolve rapidly,  expanding beyond software exploits into physical techniques such as side‑channel analysis (SCA) and fault injection (FI). Fixing hardware weaknesses late in development is costly and often impractical, and in some cases impossible once devic... » read more

HW Fingerprinting Technique for Silicon Photonic ICs Using Photonic Crystal-based Density-Controlled Patterns (U. of Florida)
By Technical Paper Link - 29 Jun, 2026 - Comments: 0

Researchers from University of Florida published a technical paper titled “Enhancing Co-packaging Optics Enabled Silicon Photonics Security Assurance Hardware Fingerprinting.” Abstract Excerpt: The paper proposes a method that “embeds two-dimensional photonic crystal (PhC) patterns” and creates a “distinctive optical signature” for device authentication. Find the technical pap... » read more

Fault Injection Framework Targets RISC-V Security Weak Spots
By - 14 Jun, 2026 - Comments: 0

Researchers from Politecnico di Torino and CEA-List published a technical paper titled “InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.” Abstract "Fault Injection Attacks (FIAs) are a significant threat to hardware security, capable of compromising systems by inducing malicious faults in computation or storage. Evaluating resilience against such attacks is chal... » read more

Building Edge AI with IP Solutions
By Cadence - 11 Jun, 2026 - Comments: 0

As AI inference moves from centralized cloud infrastructure into vehicles, factories, medical devices, and industrial systems, the decisive design challenge shifts from model quality to field-ready implementation. Deployed edge AI systems must perform reliably under a range of constraints, including fixed power budgets, stringent latency requirements, limited or intermittent cloud connectivity,... » read more

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