Chip Industry Week In Review

By The SE Staff - 31 Jul, 2026 - Comments: 1

DAC: Chips to Systems Conference The energy and buzz at this year's Design Automation Conference surprised everyone — despite initial concerns about its location in Long Beach, California, which is well off the beaten path for semiconductors. Hot topics included AI automation, multiphysics simulation, compute-in-memory, chiplets, physical AI, and the development and orchestration of AI a... » read more

Startup Funding: Q1 2026

By Jesse Allen - 13 Apr, 2026 - Comments: 0

The new year started off with a bang for private semiconductor companies, with 18 garnering mega funding rounds exceeding $100 million, and two, Rapidus and Cerebras, reaching the $1 billion mark. Predictably, the vast majority of those are either designing chips primarily for AI inference workloads or attempting to overcome bandwidth limitations by improving interconnects from the chip level t... » read more

Memory Wall Gets Higher

By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Chip Industry Week in Review

By The SE Staff - 06 Feb, 2026 - Comments: 1

Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

What Do LLMs Want from Hardware

By Geoff Tate - 08 Sep, 2025 - Comments: 0

Figure 1: Noam Shazeer, Google Gemini vice president, presented this in his Hot Chips 2025 talk. Noam Shazeer is Google’s vice president of engineering for Gemini, their LLM competitor to ChatGPT. He talked recently at Hot Chips: “Predictions for the Next Phase of AI." He has worked on LLMs for a decade since inventing the transformer model in 2017. As his slide says, LLMs can take adv... » read more

Distributing Intelligence Inside Multi-Die Assemblies

By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Physics Limits Interposer Line Lengths

By Bryon Moyer - 19 Jun, 2025 - Comments: 1

Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals... » read more

Optimizing Data Movement

By Ann Mutschler - 29 May, 2025 - Comments: 1

Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

More Data, More Redundant Interconnects

By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Die-to-die Interconnect Standards In Flux

By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

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