Chip Industry Week In Review

By The SE Staff - 31 Jul, 2026 - Comments: 1

DAC: Chips to Systems Conference The energy and buzz at this year's Design Automation Conference surprised everyone — despite initial concerns about its location in Long Beach, California, which is well off the beaten path for semiconductors. Hot topics included AI automation, multiphysics simulation, compute-in-memory, chiplets, physical AI, and the development and orchestration of AI a... » read more

Chip Industry Week In Review

By The SE Staff - 17 Jul, 2026 - Comments: 0

Advanced manufacturing, packaging Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology. UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singa... » read more

From Reactive Replacement To Predictive Planning: Unlocking Probe Card Intelligence With Real-Time Data

By Arik Peltz - 07 Jul, 2026 - Comments: 0

Probe cards are among the most critical — and costly — assets in wafer test. Even if production line typically prepares on-demand spares, unexpected failure can cause significant downtime and production loss. One of the most persistent challenges is tip-burn degradation: gradual probe tips wear that ultimately leads to failure. A new technical initiative explores whether DC profiling dat... » read more

When The Test Cell Lies

By Gregory Haley - 07 Jul, 2026 - Comments: 0

Key Takeaways: A marginal test result can be electrically valid and still diagnostically misleading because the socket, load board, and thermal loop are now part of the measurement. Separating device drift from test-cell drift depends on tracking margins, variance, and calibration trends rather than bins alone. In advanced packages, a false pass destroys value downstream, a false f... » read more

Chip Industry Week In Review

By The SE Staff - 26 Jun, 2026 - Comments: 0

IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test

By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp

By Anne Meixner - 09 Jun, 2026 - Comments: 0

Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

Chip Industry Week In Review

By The SE Staff - 22 May, 2026 - Comments: 0

Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Test Distribution Evolves To Meet AI Challenges

By Fabio Pizza - 12 May, 2026 - Comments: 0

The proliferation of artificial intelligence (AI) is driving rapid acceleration of the semiconductor market, which analysts now predict will reach $1 trillion this year. Many semiconductor devices will be the GPUs that populate the data centers that run AI workloads. Driven by strong, sustained investments from hyperscaler operators, high-performance computing (HPC)/AI data centers are expected... » read more

AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

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Chip Industry Week In Review

Chip Industry Week In Review

From Reactive Replacement To Predictive Planning: Unlocking Probe Card Intelligence With Real-Time Data

When The Test Cell Lies

Chip Industry Week In Review

Why Analog And Mixed-Signal Chips Resist Adaptive Test

Co-Packaged Optics Testing Faces Steep Data Center Ramp

Chip Industry Week In Review

Test Distribution Evolves To Meet AI Challenges

AI Accelerator Testing Depends On DFT Innovations

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