tag: SRAM

Certified Automotive-Grade PUF IP: Unclonable Silicon Identity For Safety And Security
By Geert-Jan Schrijen - 06 Aug, 2026 - Comments: 0

By Geert-Jan Schrijen, Peter Simons, and Dana Neustadter Today's vehicles are quickly becoming intelligent Physical AI platforms. Capabilities such as advanced driver assistance systems (ADAS), autonomous driving, intelligent cabins, robotic mobility, EV power management, and vehicle-to-everything (V2X) communications now lean heavily on AI models to perceive, reason, and act in the physical... » read more

Processing-in-Memory Simulator Supporting 11 Memory Technologies (Riken, Keio,Los Alamos, ORNL)
By Technical Paper Link - 05 Aug, 2026 - Comments: 0

Researchers from RIKEN Center for Computational Science, Keio University, Los Alamos National Laboratory, and Oak Ridge National Laboratory published a technical paper titled “PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory.” Abstract Excerpt: "Processing-in-Memory addresses the memory wall by co-locating computation with memory, but because real P... » read more

Can Fine-Pitch Hybrid Bonding Go High Volume?
By Gregory Haley - 16 Jul, 2026 - Comments: 0

Key Takeaways: Fine-pitch hybrid bonding extends a proven production technology into a manufacturing regime with much smaller margins for particles, surface variation, distortion, and placement error. Die-to-wafer integration allows known-good-die selection, but it exchanges wafer-level parallelism for repeated handling, alignment, and bonding operations. Reaching high volume will de... » read more

3nm GAA-FET SRAM Review Evaluates Self-Heating And Radiation Hardness (SJSU, Sandia)
By Technical Paper Link - 12 Jul, 2026 - Comments: 0

Researchers from San Jose State University and Sandia National Laboratories published a technical paper titled “Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques.” Abstract Excerpt: “In addition to the traditional bottom dielectric isolation (BDI), which isolates the source/drain (S/D) from the substrate (dubbed SD-BDI),... » read more

Reducing Avoidable Memory Trips In HBM Systems
By André Bonnardot - 25 Jun, 2026 - Comments: 0

Picture a highway during rush hour. When a road has limited capacity, traffic backs up quickly because only so many cars can move through at once. Adding more lanes increases capacity, but it does not always guarantee a smoother commute. If cars keep flooding onto the highway, if exits are poorly placed, or if drivers have to stay on the road for long distances, congestion can still build. More... » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Large-scale, SRAM-based LLM Inference Deployment (Groq)
By Technical Paper Link - 21 May, 2026 - Comments: 0

A new technical paper, "SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving," was published by researchers at Nvidia, with work done while at Groq. Abstract "The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV caches, creating a memory bandwidth b... » read more

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill
By HJ Kim - 21 May, 2026 - Comments: 0

As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Optimizing In-Memory AI Accelerators Across Multiple Workloads (KAUST, Compumacy)
By Technical Paper Link - 06 Mar, 2026 - Comments: 0

Researchers from KAUST and Compumacy for Artificial Intelligence Solutions have released “Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators”. Abstract “Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, lea... » read more

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