Author's Latest Posts


Full Vehicle Integration Testing via Cloud-based Electronics Digital Twins at Volvo Cars


Discover how Volvo Cars accelerated development of its software defined vehicle platform by creating a full cloud-based electronics digital twin using Synopsys Silver virtual ECUs, QNX OS virtualization, and AWS infrastructure. This success story highlights how early integration testing, continuous validation, and scalable simulation environments dramatically reduce downstream integration risk... » read more

Silicon Starts with Proven IP: eBook


AI-driven complexity and advanced nodes are increasing silicon design risk and time pressure. This ebook shows why IP strategy is now an architectural decision and how silicon-proven IP reduces integration risk, improves first-pass success, and accelerates time-to-market. Learn how a unified portfolio of foundation, interface, and security IP enables scalable, high-performance designs acr... » read more

Co-Packaged Optics for Multi-Die Designs


As bandwidth scales to 800G and 1.6T, electrical interconnects and pluggable optics reach limits in power, distance, and signal integrity. Co‑packaged optics (CPO) addresses these challenges by moving optical interconnect closer to silicon, reducing electrical path length, lowering power per bit, and enabling higher bandwidth density. This white paper explains why CPO is emerging now, how it ... » read more

PCIe 7.0 in Practice: Design Considerations for Storage, Networking, and AI


Gain technical insights from our PCIe 7.0 white paper, focused on advanced interconnect solutions for high-performance systems. This guide will help you: Understand Key Advancements: Dive into PCIe 7.0’s doubled signaling rates, FLIT-based architecture, and enhanced IP for bandwidth and protocol efficiency. Explore Domain-Specific Applications: See how PCIe 7.0 IP elevates throughpu... » read more

Re-Engineering Engineering for Automotive with Electronics Digital Twins for the SDV Era


As vehicles become software-defined, traditional development approaches can’t keep pace with growing complexity, shorter innovation cycles, and rising validation demands. By leveraging the Synopsys eDT Platform for Automotive, companies can accelerate software bring-up, enhance collaboration, reduce prototyping costs, and ensure higher safety and reliability across the vehicle lifecycle. ... » read more

How to Create Efficient Bump and TSV Plans for Multi-Die Designs


In a multi-die design logical and physical interconnectivity between dies (or a die and interposer or other substrate) is achieved through microbumps or hybrid bonding pads between contacting dies. Today’s multi-die designs can have hundreds of thousands or millions of bumps, and this number will be increasing dramatically in the future, as hybrid bonding technology greatly reduces the pi... » read more

Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design


Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability across key applications such as mobile, IoT, AI, HPC, automotive, crypto, and networking. Why read this digest... » read more

Beating the Edge AI Power Wall with Low Voltage Foundation IP


Edge AI is pushing the limits of power efficiency as intelligence moves closer to the data source. Designing for ultra-low voltage operation is now essential to achieve optimal performance-per-watt—but it introduces significant complexity in modeling, variation, and design predictability. In this white paper, discover how a unified, silicon-proven Foundation IP platform approach enables relia... » read more

Multiphysics Fusion Technology for Multi-Die Designs Explained


Multiphysics issues are no longer a late-stage problem. Multi-die designs introduce tightly coupled electrical, thermal, electromagnetic, and electromechanical challenges that impact performance and reliability. This eBook shows why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through signoff. What You�... » read more

Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s


Scaling raw lane speed without rethinking controller microarchitecture leads to diminishing returns. It introduces multistream architecture, a controller‑level re‑architecture designed to sustain effective bandwidth under mixed and small‑packet workloads. This paper examines the architectural inflection point at PCIe 6.0, details transmit‑ and receive‑side changes required for multist... » read more

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