Liewei Bao

Processor: A 64-Core SoC with Mesh Interconnect

Centralized monolithic processor designs, such as single core and shared bus structures, are not ... more Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore designs becoming the norm [1-3]. Research highlights the benefits of mesh networks connecting these cores. [4,5]. The TILE64™ processor [6] is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. Figure 4.4.1 shows a block diagram with 64 tile processors arranged in an 8×8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux. Chip peak memory bandwidth is over 25GB/s using four 72-bit 800MHz DDR2 interfaces. Two PCI-e ×4 interfaces, two XAUI interfaces and two RGMII interfaces supply over 40Gb/s of I/O bandwidth. Flexible general purpose I/O ports and low-speed interfaces provide seamless integration with a variety of systems.

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Processor: A 64-Core SoC with Mesh Interconnect

Centralized monolithic processor designs, such as single core and shared bus structures, are not ... more Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore designs becoming the norm [1-3]. Research highlights the benefits of mesh networks connecting these cores. [4,5]. The TILE64™ processor [6] is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. Figure 4.4.1 shows a block diagram with 64 tile processors arranged in an 8×8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux. Chip peak memory bandwidth is over 25GB/s using four 72-bit 800MHz DDR2 interfaces. Two PCI-e ×4 interfaces, two XAUI interfaces and two RGMII interfaces supply over 40Gb/s of I/O bandwidth. Flexible general purpose I/O ports and low-speed interfaces provide seamless integration with a variety of systems.

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TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Centralized monolithic processor designs, such as single core and shared bus structures, are not ... more Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore designs becoming the norm [1-3]. Research highlights the benefits of mesh networks connecting these cores. [4,5]. The TILE64™ processor [6] is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. Figure 4.4.1 shows a block diagram with 64 tile processors arranged in an 8×8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux. Chip peak memory bandwidth is over 25GB/s using four 72-bit 800MHz DDR2 interfaces. Two PCI-e ×4 interfaces, two XAUI interfaces and two RGMII interfaces supply over 40Gb/s of I/O bandwidth. Flexible general purpose I/O ports and low-speed interfaces provide seamless integration with a variety of systems.

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On-Chip Interconnection Architecture of the Tile Processor

IEEE Micro, 2007

integrated onto a single die increases, the design space for interconnecting these cores becomes ... more integrated onto a single die increases, the design space for interconnecting these cores becomes more fertile. One manner of interconnecting the cores is simply to mimic multichip, multiprocessor computers of the past. Following past practice, simple busbased shared-memory multiprocessors can be integrated onto a single piece of silicon. But, in taking this well-traveled route, we squander the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used 1D rings, but rings do not scale well either, because their bisection bandwidth does not increase with the addition of more cores. This article describes the Tile Processor and its on-chip interconnect network, iMesh, which is a departure from the traditional bus-based multicore processor.

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4.4 TILE64 TM Processor: A 64-Core SoC with Mesh Interconnect

Centralized monolithic processor designs, such as single core and shared bus structures, are not ... more Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore designs becoming the norm [1-3]. Research highlights the benefits of mesh networks connecting these cores. [4,5]. The TILE64™ processor [6] is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. Figure 4.4.1 shows a block diagram with 64 tile processors arranged in an 8×8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux. Chip peak memory bandwidth is over 25GB/s using four 72-bit 800MHz DDR2 interfaces. Two PCI-e ×4 interfaces, two XAUI interfaces and two RGMII interfaces supply over 40Gb/s of I/O bandwidth. Flexible general purpose I/O ports and low-speed interfaces provide seamless

Second at 1GHZ

...... As the number of processor cores integrated onto a single die increases, the design space ... more ...... As the number of processor cores integrated onto a single die increases, the design space for interconnecting these cores becomes more fertile. One manner of interconnecting the cores is simply to mimic multichip, multiprocessor computers of the past. Following past practice, simple busbased shared-memory multiprocessors can be integrated onto a single piece of silicon. But, in taking this well-traveled route, we squander the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used 1D rings,

34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021

Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with t... more Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with the potential to significantly reduce the delay between symptom onset and initiation of therapy. Conventional POCUS systems are based on piezoelectric transducers and cable-connected electronics, which require a costly manufacturing process and usually come with an undesirably limited channel count. Such devices typically serve a specific subset of clinical applications, as imaging at different body parts calls for different ultrasound frequencies that are beyond the bandwidth of a single piezoelectric transducer. To enable whole-body imaging, multiple probes with different frequencies, apertures and beamforming (BF) methods are generally required. This further limits the affordability and accessibility of POCUS. Recent advances in micromachined ultrasound transducers (MUTs) have offered an alternative path to addressing these challenges. However, previous attempts to integrate MUTs with ...

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Ultrasound-on-chip platform for medical imaging, analysis, and collective intelligence

Proceedings of the National Academy of Sciences

Over the past half-century, ultrasound imaging has become a key technology for assessing an ever-... more Over the past half-century, ultrasound imaging has become a key technology for assessing an ever-widening range of medical conditions at all stages of life. Despite ultrasound’s proven value, expensive systems that require domain expertise in image acquisition and interpretation have limited its broad adoption. The proliferation of portable and low-cost ultrasound imaging can improve global health and also enable broad clinical and academic studies with great impact on the fields of medicine. Here, we describe the design of a complete ultrasound-on-chip, the first to be cleared by the Food and Drug Administration for 13 indications, comprising a two-dimensional array of silicon-based microelectromechanical systems (MEMS) ultrasonic sensors directly integrated into complementary metal–oxide–semiconductor-based control and processing electronics to enable an inexpensive whole-body imaging probe. The fabrication and design of the transducer array with on-chip analog and digital circuit...

Memory Control System with Incrementer for Generating Spectulative Addresses

Managing memory requests based on priority

Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design

Configuring routing in mesh networks

Memory controller with prefetching capability

Memory control system with incrementer for generating speculative addresses

Networks of the Tilera Multicore Processor

Chapman & Hall/CRC Computational Science, 2010

Buffering system bus for external-memory access

TILE64 - Processor: A 64Core SoC with Mesh Interconnect

The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range ... more The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. A figure shows a block diagram with 64 tile processors arranged in an 8x8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux.

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