Mariusz Rawski

Warsaw University of Technology, Faculty of Electronics and Information Technology, Faculty Member

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Muhammad Faraz Hyder

Abdulhakim Sabur

Arizona State University

Carnegie Mellon University

Khalid Alhamed

Jin Gon Shon

Korea National Open University

Dilli Sharma

University of Toronto

Sakir Sezer

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Papers by Mariusz Rawski

A Survey on Moving Target Defense for Networks: A Practical View

Electronics

The static nature of many of currently used network systems has multiple practical benefits, incl... more The static nature of many of currently used network systems has multiple practical benefits, including cost optimization and ease of deployment, but it makes them vulnerable to attackers who can observe from the shadows to gain insight before launching a devastating attack against the infrastructure. Moving target defense (MTD) is one of the emerging areas that promises to protect against this kind of attack by continuously shifting system parameters and changing the attack surface of protected systems. The emergence of network functions virtualization (NFV) and software-defined networking (SDN) technology allows for the implementation of very sophisticated MTD techniques. Furthermore, the introduction of such solutions as field-programmable gate array (FPGA) programmable acceleration cards makes it possible to take the MTD concept to the next level. Applying hardware acceleration to existing concepts or developing new, dedicated methods will offer more robust, efficient, and secure...

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Comparison of Hash Functions for Network Traffic Acquisition Using a Hardware-Accelerated Probe

Electronics

In this article we address the problem of efficient and secure monitoring of computer network tra... more In this article we address the problem of efficient and secure monitoring of computer network traffic. We proposed, implemented, and tested a hardware-accelerated implementation of a network probe, using the DE5-Net FPGA development platform. We showed that even when using a cryptographic SHA-3 hash function, the probe uses less than 17% of the available FPGA resources, offering a throughput of over 20 Gbit/s. We have also researched the problem of choosing an optimal hash function to be used in a network probe for addressing network flows in a flow cache. In our work we compared five 32-bit hash functions, including two cryptographic ones: SHA-1 and SHA-3. We ran a series of experiments with various hash functions, using traffic replayed from the CICIDS 2017 dataset. We showed that SHA-1 and SHA-3 provide flow distributions as uniform as the ones offered by the modified Vermont hash function proposed in 2008 (i.e., with low means and standard deviations of the bucket occupation), y...

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VHS-22 – A Very Heterogeneous Set of Network Traffic Data for Threat Detection

EICC 2022: Proccedings of the European Interdisciplinary Cybersecurity Conference

Researching new methods of detecting network threats, e.g., malwarerelated, requires large and di... more Researching new methods of detecting network threats, e.g., malwarerelated, requires large and diverse sets of data. In recent years, a variety of network traffic datasets have been proposed, which have been intensively used by the research community. However, most of them are quite homogeneous, which means that detecting threats using these data became relatively easy, allowing for detection accuracy close to 100%. Therefore, they are not a challenge anymore. As a remedy, in this article we propose a VHS-22 dataset-a Very Heterogeneous Set of network traffic data. We prepared it using a software network probe and a set of existing datasets. We describe the process of dataset creation, as well as its basic statistics. We also present initial experiments on attack detection, which yielded lower results than for other datasets. We claim that the data in the VHS-22 dataset are more demanding, and therefore that our dataset can better stimulate further progress in detecting network threats. CCS CONCEPTS • Security and privacy → Network security.

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Hardware / Software Co-design of DTW procedure in programmable devices

Realizacja jednostki wspomagającej kryptoanalizę szyfrów opartych na krzywych eliptycznych w strukturach reprogramowalnych

Nowe metody sprzętowo-programowego przetwarzania sygnałów i obrazów dla potrzeb systemów informacyjnych

FPGA Implementation of Memory Management for Multigigabit Traffic Monitoring

Network traffic monitoring in high-speed links is a challenging task. One of the main bottlenecks... more Network traffic monitoring in high-speed links is a challenging task. One of the main bottlenecks of such solution are very often the memory bandwidth and its capacity. This usually forces the designers to apply traffic sampling to handle high rates and extreme traffic mixes. This paper presents a novel approach to a memory management system for network flow monitoring designed for FPGA implementation. Hardware memory management unit offers efficiency that allows its application in multi-gigabit networks, while programmable technology delivers flexibility, that allows to customize solution for specific needs.

System typu SoC do kryptoanalizy szyfrów opartych na krzywych eliptycznych

B06: Advanced synthesis of digital filters based on distributed arithmetic concept for FPGAs

IFAC Proceedings Volumes, 2004

This paper presents the application of distributed arithmetic in implementation of digital filter... more This paper presents the application of distributed arithmetic in implementation of digital filter in FPGA structures. Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. In this paper an application of the functional decomposition based method to LUT blocks optimisation and mapping has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures, thus it allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

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B01: The novel approach to FSM synthesis targeted FPGA architectures

IFAC Proceedings Volumes, 2004

This paper presents the novel approach to logic synthesis of finite state machines for FPGA archi... more This paper presents the novel approach to logic synthesis of finite state machines for FPGA architectures. Traditional methods are based on two steps: internal states encoding and then mapping of encoded state transition table into target architecture. In case of FPGAs the functional decomposition is recognized as the most efficient method of digital circuits' implementation. However none of known state encoding algorithms can be considered as the best method to be used with the functional decomposition. In this paper the concept of symbolic functional decomposition is introduced. In this method no separate encoding step is required. Symbolic functional decomposition accepts FSM with symbolic states and performs decomposition introducing such state encoding that guarantees the best solution.

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Decomposition-Based Methods for FSM Implementation

Studies in Systems, Decision and Control, 2015

Designing a complex digital system requires an effective method for modeling the sequential part ... more Designing a complex digital system requires an effective method for modeling the sequential part of the system. One of the methods is the Finite State Machine based modeling. The implementation efficiency of the sequential part of the designed system has usually a great impact on the processing performance of the whole digital system. Petri nets, which are another method of modeling the sequential part of systems, can also be transformed into FSM-based models. Thus, development of effective synthesis methods for FSM implementation is very important. Digital systems are often implemented in FPGA architectures. Because of their specific structure, the most efficient synthesis methods are based on functional decomposition. This chapter discusses decomposition-based methods for FSM implementation targeting programmable structures.

Reversible logic synthesis of boolean functions using functional decomposition

2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), 2015

Reversible logic circuits are one of the solutions to the problem of conventional microelectronic... more Reversible logic circuits are one of the solutions to the problem of conventional microelectronic technology reaching its limits. Unfortunately, efficient reversible system design requires different approaches than conventional solutions; the current methods of reversible function synthesis have certain limitations, including their complexity and scalability. This paper presents the application of functional decomposition, developed for conventional logic synthesis, as a potentially crucial step in synthesis of reversible logic. A decomposition of a Boolean function into a network of smaller sub-functions, subsequently synthesized into reversible blocks and composed into a reversible system, often yields better results than direct reversible synthesis of the original Boolean function. The experimental results presented in this paper demonstrate the potential of the proposed approach.

Synteza Logiczna W Projektowaniu Układów Cyfrowego Przetwarzania Sygnałów

Zależności Funkcjonalne I Ich Miary W Syntezie Logicznej Dla Układów Fpga

Akceleracja algorytmów kryptologicznych z wykorzystaniem struktur programowalnych

Comparison of different decomposition techniques of a digital circuit-a study case

Implementacja sprzętowa dwuwymiarowej transformacji falkowej w układach FPGA

Digital Systems Design

Application of functional decomposition in synthesis of boolean function sets

Proceedings of 19th International Conference on Systems Engineering, ICSEng 2008, 2008

ABSTRACT The paper presents a new disjoint functional decomposition method for set of Boolean fun... more ABSTRACT The paper presents a new disjoint functional decomposition method for set of Boolean functions specified by separate truth tables. The functional decomposition has important applications in many fields of modern engineering and science (FPGA synthesis, information systems, neural networks and many others). The presented algorithm is dedicated to multi-output Boolean functions. The concept is based on dividing the complex multi-output function into single output functions and then utilizing common information needed by these functions to construct functional decomposition. The presented method was implemented in prototype tool and the results are presented in the paper.

A graph-based approach to symbolic functional decomposition of finite state machines

Proceedings of 19th International Conference on Systems Engineering, ICSEng 2008, 2008

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A Survey on Moving Target Defense for Networks: A Practical View

Electronics

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Comparison of Hash Functions for Network Traffic Acquisition Using a Hardware-Accelerated Probe

Electronics

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VHS-22 – A Very Heterogeneous Set of Network Traffic Data for Threat Detection

EICC 2022: Proccedings of the European Interdisciplinary Cybersecurity Conference

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Hardware / Software Co-design of DTW procedure in programmable devices

Realizacja jednostki wspomagającej kryptoanalizę szyfrów opartych na krzywych eliptycznych w strukturach reprogramowalnych

Nowe metody sprzętowo-programowego przetwarzania sygnałów i obrazów dla potrzeb systemów informacyjnych

FPGA Implementation of Memory Management for Multigigabit Traffic Monitoring

System typu SoC do kryptoanalizy szyfrów opartych na krzywych eliptycznych

B06: Advanced synthesis of digital filters based on distributed arithmetic concept for FPGAs

IFAC Proceedings Volumes, 2004

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B01: The novel approach to FSM synthesis targeted FPGA architectures

IFAC Proceedings Volumes, 2004

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Decomposition-Based Methods for FSM Implementation

Studies in Systems, Decision and Control, 2015

Reversible logic synthesis of boolean functions using functional decomposition

2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), 2015

Synteza Logiczna W Projektowaniu Układów Cyfrowego Przetwarzania Sygnałów

Zależności Funkcjonalne I Ich Miary W Syntezie Logicznej Dla Układów Fpga

Akceleracja algorytmów kryptologicznych z wykorzystaniem struktur programowalnych

Comparison of different decomposition techniques of a digital circuit-a study case

Implementacja sprzętowa dwuwymiarowej transformacji falkowej w układach FPGA

Digital Systems Design

Application of functional decomposition in synthesis of boolean function sets

Proceedings of 19th International Conference on Systems Engineering, ICSEng 2008, 2008

A graph-based approach to symbolic functional decomposition of finite state machines

Proceedings of 19th International Conference on Systems Engineering, ICSEng 2008, 2008

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