Changeset 2823149

Timestamp:

11/23/2022 08:04:38 PM (3 years ago)

Author:

mseminatore

Message:

added SystemVerilog support

Location:

add-verilog-brush-syntaxhighlighter-evolved/trunk

Files:

• readme.txt (modified) (1 diff)
• shBrushVerilog.js (modified) (1 diff)

add-verilog-brush-syntaxhighlighter-evolved/trunk/readme.txt

@@ -4 +4 @@
 Tags: syntaxhighlighter, verilog
 Requires at least: 4.7
-Tested up to: 5.8
-Stable tag: 1.0.15
+Tested up to: 6.1.1
+Stable tag: 1.0.16
 Requires PHP: 7.0
 License: GPLv3

add-verilog-brush-syntaxhighlighter-evolved/trunk/shBrushVerilog.js

@@ -7 +7 @@
     {
     
-        var datatypes = 'wire reg integer real time ';
+        var datatypes = 'wire reg integer real time logic ';
 
         var keywords =  'always assign begin case casex casez default else end endcase endfunction endmodule endprimitive endtable endtask ' +
                         'for forever function if initial inout input localparam module negedge output parameter posedge primitive ' +
-                        'repeat table task timescale while';
+                        'repeat table task timescale while always_ff always_comb always_latch typedef enum ';
                     
         var functions = 'and or nand nor not xor ';