Guojie Luo

Peking University, Computer Science, Faculty Member

Peking University, Electrical Engineering & Computer Sciences, Department Member

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Guojie Luo received his B.S. degree (with honors) in Computer Science from Peking University, Beijing, China in 2005, the M.S. and Ph.D. degrees in Computer Science from the University of California, Los Angeles in 2008 and 2011, respectively. He has won the 2013 ACM SIGDA Outstanding PhD Dissertation Award in Electronic Design Automation and the 2017 ASP-DAC Ten-Year Retrospective Most Influential Paper Award. He joined the faculty of Center for Energy-Efficient Computing and Applications (CECA), School of Electrical Engineering and Computer Science (EECS) at Peking University from August 2011. His current research interests include electronic design automation, heterogeneous computing with FPGAs and emerging devices, and medical imaging analytics.

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Lafifa Jamal

University of Dhaka, Bangladesh

Alan Schwartz

University of Illinois at Chicago

Mitchell Thornton

Southern Methodist University

Lisa Gualtieri

Tufts University

A N K Zaman

Rajshahi University

Omid Pournik

Iran University of Medical Sciences

Domingo Liotta

UNIVERSIDAD DE MORON

Walid Issa

University of Exeter

Ahmed Abid

Middle Technical University

Izet Masic, MD, PhD, FWAAS, FEASA, FIAHSI, FEFMI, FACMI

University of Sarajevo

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Papers by Guojie Luo

Feasibility study of practical vital sign detection using millimeter-wave radios

CCF Transactions on Pervasive Computing and Interaction, Nov 15, 2021

TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021

Transposed convolution is a learnable up-sampling operator widely-used in deep neural networks. I... more Transposed convolution is a learnable up-sampling operator widely-used in deep neural networks. It up-samples the input activations to generate useful information in applications like style transfer and super resolution. There exists a rising demand for accelerating transposed convolution layers since they occupy a large portion of computation in GAN-like networks.

Erratum to: NFAT5-mediated CACNA1C expression is critical for cardiac electrophysiological development and maturation

Journal of molecular medicine (Berlin, Germany), 2016

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Evaluating Low-Memory GEMMs for Convolutional Neural Network Inference on FPGAs

FPGAs are becoming significant for implementing low-latency convolutional neural networks, becaus... more FPGAs are becoming significant for implementing low-latency convolutional neural networks, because of performance demands and power constraints. Conventional implementations of convolutional layers are usually direct convolution, involving nested loops over channels, feature maps, and filters. Explicit general matrix multiplications (GEMMs) cost extra memory space, and the limited on-chip RAMs prevent an efficient GEMM-based implementation. In this paper, we evaluate a low-memory method of GEMMs on FPGAs based systolic arrays. We design a novel accelerator to save the bandwidth and increase the parallelism. We evaluate our design on MobileNet V1 and Inception V4. Our implementation achieves a throughput of around 3.5 TOP/s for both models. We also reduce the memory usage by 21% compared to explicit GEMM implementation for MobileNet V1 and 44% for Inception V4.

Adaptive-precision framework for SGD using deep Q-learning

Proceedings of the International Conference on Computer-Aided Design

Stochastic gradient descent (SGD) is a widely-used algorithm in many applications, especially in ... more Stochastic gradient descent (SGD) is a widely-used algorithm in many applications, especially in the training process of deep learning models. Low-precision implementation for SGD has been studied as a major acceleration approach. However, if not appropriately used, low-precision implementation can deteriorate its convergence because of the rounding error when gradients become small near a local optimum. In this work, to balance throughput and algorithmic accuracy, we apply the Q-learning technique to adjust the precision of SGD automatically by designing an appropriate decision function. The proposed decision function for Q-learning takes the error rate of the objective function, its gradients, and the current precision configuration as the inputs. Q-learning then chooses proper precision adaptively for hardware efficiency and algorithmic accuracy. We use reconfigurable devices such as FPGAs to evaluate the adaptive precision configurations generated by the proposed Q-learning method. We prototype the framework using LeNet-5 model with MNIST and CIFAR10 datasets and implement it on a Xilinx KCU1500 FPGA board. In the experiments, we analyze the throughput of different precision representations and the precision-selection of our framework. The results show that the proposed framework with adapative precision increases the throughput by up to 4.3× compared to the conventional 32-bit floating point setting, and it achieves both the best hardware efficiency and algorithmic accuracy.

Session details: Routing with Cell Movement (Virtual)

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction

2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020

In this work, we aim to accelerate the iterative reconstruction (IR) algorithm used for 3D low do... more In this work, we aim to accelerate the iterative reconstruction (IR) algorithm used for 3D low dose computer tomography (LDCT) reconstruction to reduce the long execution time from an order of several hours on CPU to a few minutes. IR algorithms such as Mumford-Shah (MS) regularization can be used to get high-quality images even though the signal-noise ratio (SNR) of low dose projection data is low. However, IR is a computation and memory-intensive application and the long execution time precludes its clinical application. We adopt the ray-based parallel algorithm and designed a customized processing engine with multiple parallel processing elements (PEs) on field-programmable gate array (FPGA) to improve the computation efficiency. To reduce resource utilization, we proposed a best-first search algorithm combined with pruning to find the optimal bit width for fixed-point reconstruction. Besides, an offline memory optimization framework based on a greedy based clustering algorithm is proposed to reduce external memory bandwidth requirement and balance the workload of parallel PEs. Experiments on a 3D Shepp-Logan phantom show 2.81X and 1.91X speedup over the state of art single GPU and FPGA implementation.

Agile design of DCT circuit on soft CGRA

International Conference on High Performance Computing and Communication (HPCCE 2021), 2022

High-level synthesis technology is a technology for circuit design using high-level languages suc... more High-level synthesis technology is a technology for circuit design using high-level languages such as C, C++, or System C. This design method is suitable for algorithm engineers to implement calculation prototypes and is not suitable for hardware engineers to design circuits from the register transfer level. In addition, from the perspective of agile development and code reuse, C, C++, and System C are far from another hardware description language, Chisel. However, there are relatively few electronic design automation tools for Chisel, so we propose a circuit design flow based on CGRA hardware, in which Chisel designs the PE unit of CGRA. However, Chisel has few electronic design automation tools, so a circuit design flow based on CGRA is proposed. Dedicated data flow graph generation tools and typical coarse-grained reconfigurable arrays are implemented for this design flow. This article describes a design process based on CGRA and compares the design process with HLS through the DCT circuit design process. Through the experimental comparison of the two circuit implementation processes, it is found that, first of all, the correctness of the CGRA-based design process and the availability of data flow diagram generation tools. Secondly, from a design point of view, the use of Chisel will increase the overall development speed and increase the reusability of design files. Finally, from the perspective of toolchains, part of the tools in the new design process uses open-source toolchains, which reduces the cost of using toolchains and promotes the development of toolchains to a certain extent.

8B-1 Thermal-Aware 3D IC Placement Via Transformation

Abstract- 3D IC technologies can help to improve circuit performance and lower power consumption ... more Abstract- 3D IC technologies can help to improve circuit performance and lower power consumption by reducing wirelength. Also, 3D IC technology can be used to realize heterogeneous system-on-chip design, by integrating different modules together with less interference with each other. In this paper, we propose a novel thermal-aware 3D cell placement approach, named T3Place, based on transforming a 2D placement with good wirelength to a 3D placement, with the objectives of half-perimeter wirelength, through-the-silicon (TS) via number and temperature. T3Place is composed of two steps, transformation from a 2D placement to a 3D placement and the refinement of the resulting 3D placement. We proposed and compared several different transformation techniques, including local stacking transformation (LST), folding-2, folding-4 and window-based stacking/folding transformation, and concluded that (i) LST can generate 3D placements with the least wirelength, (ii) the folding-based transformat...

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Introduction of Indoor Map Construction

Smartphone-Based Indoor Map Construction, 2018

We describe the motivation and background of map construction for ubiquitous indoor location-base... more

Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping

2021 58th ACM/IEEE Design Automation Conference (DAC), 2021

Coarse-grained reconfigurable architecture (CGRA) is a promising programmable device with high pe... more Coarse-grained reconfigurable architecture (CGRA) is a promising programmable device with high performance and power efficiency. The CGRA compilation problem is to map an application onto a 3D time-space model of CGRA. Adding the circuitry of synchronizers can relax the mapping constraint for data alignment in time; and thus, it significantly influences the compilation performance. However, data-departure synchronizers may be infeasible, because an output value may be used multiple times and has a high fan-out. Instead, data-arrival synchronizers can further improve performance and mappability of CGRAs with acceptable overhead, compared to the synchronization methods based on detour routing, register files, and FIFO.In this work, we design two kinds of data-arrival synchronizers and formulate them in an integer linear programming (ILP) based mapping approach. The separate ILP formulations of placement and routing speed up the architecture exploration with synchronizers by up to 3.03x. The experimental study shows that data-arrival synchronizers improve CGRA performance by 19.8% on average. The results of our quantitative study show that synchronizers also improve the mapping success rate by 1.91x on average. In conclusion, CGRAs with appropriate synchronizers have better mappability while using fewer resources.

cuMBIR

Proceedings of the 2018 International Conference on Supercomputing, 2018

Low-dose X-ray computed tomography (XCT) is a popular imaging technique to visualize the inside s... more Low-dose X-ray computed tomography (XCT) is a popular imaging technique to visualize the inside structure of object non-destructively. Model-based Iterative Reconstruction (MBIR) method can reconstruct high-quality image but at the cost of large computational demands. Therefore, MBIR often resorts to the platforms with hardware accelerators such as GPUs to speed up the reconstruction process. For MBIR, the reconstruction process is to minimize an objective function by updating image iteratively. The X-ray source emits large amounts of X-rays from various views to cover the object as much as possible. Different X-rays always have complex and irregular geometric relationship. This inherent irregularity makes the minimization process of the objective function on GPUs very challenging. First, different implementations of the minimization of objective function have different impacts on the convergence and GPU resource utilization. To this end, we explore different solvers to the minimization problem and different parallelism granularities for GPU kernel design. Second, the complex and irregular geometric relationship of X-rays introduces irregular memory behaviors. Two nearby X-rays may intersect and thus incur memory collisions, while two far away X-rays may incur non-coalesced memory accesses. We design a unified thread mapping algorithm to guide the mapping from X-rays to threads, which can optimize the memory collisions and non-coalesced memory accesses together. Finally, we present a series of architecture level optimizations to fully release the horse power of GPUs. Evaluation results demonstrate that cuMBIR can achieve 1.48X speedup over the state-of-the-art implementation on GPUs.

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Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020

Routing is a very complex process in the field programmable gate array (FPGA) CAD flow. The incre... more Routing is a very complex process in the field programmable gate array (FPGA) CAD flow. The increase of both FPGA size and design complexity leads to a long routing time hindering the productivity. In this article, we propose a more effective parallel router that combines static and dynamic load balance in parallel routing for FPGAs. First, we explore hierarchical region partitioning to assign routing tasks to different cores for static load balance. Then, we coordinate message propagation and task migration at runtime so that load balance between cores can be dynamically maintained in parallel routing. Finally, we combine static and dynamic load balance in the parallel routing for a higher degree of parallelism. Our parallel router performs on the multicore distributed-memory systems and the communication between cores is through message passing interface messages. We demonstrate the effectiveness of our parallel router using large-scale Titan designs. On average, our parallel router can scale up to 32 cores to achieve about $17\times $ speedup with slight loss of quality, compared with the latest VTR 8 router.

Multi-Story Indoor Floor Plan Reconstruction via Mobile Crowdsensing

IEEE Transactions on Mobile Computing, 2016

The lack of floor plans is a critical reason behind the current sporadic availability of indoor l... more The lack of floor plans is a critical reason behind the current sporadic availability of indoor localization service. Service providers have to go through effort-intensive and time-consuming business negotiations with building operators, or hire dedicated personnel to gather such data. In this paper, we propose Jigsaw, a floor plan reconstruction system that leverages crowdsensed data from mobile users. It extracts the position, size, and orientation information of individual landmark objects from images taken by users. It also obtains the spatial relation between adjacent landmark objects from inertial sensor data, then computes the coordinates and orientations of these objects on an initial floor plan. By combining user mobility traces and locations where images are taken, it produces complete floor plans with hallway connectivity, room sizes, and shapes. It also identifies different types of connection areas (e.g., escalators and stairs) between stories, and employs a refinement algorithm to correct detection errors. Our experiments on three stories of two large shopping malls show that the 90-percentile errors of positions and orientations of landmark objects are about 1 $ 2m and 5 $ 9 , while the hallway connectivity and connection areas between stories are 100 percent correct.

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VeTrack

Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems, 2015

Although location awareness and turn-by-turn instructions are prevalent outdoors due to GPS, we a... more Although location awareness and turn-by-turn instructions are prevalent outdoors due to GPS, we are back into the darkness in uninstrumented indoor environments such as underground parking structures. We get confused, disoriented when driving in these mazes, and frequently forget where we parked, ending up circling back and forth upon return. In this paper, we propose VeTrack, a smartphone-only system that tracks the vehicle's location in real time using the phone's inertial sensors. It does not require any environment instrumentation or cloud backend. It uses a novel "shadow" tracing method to accurately estimate the vehicle's trajectories despite arbitrary phone/vehicle poses and frequent disturbances. We develop algorithms in a Sequential Monte Carlo framework to represent vehicle states probabilistically, and harness constraints by the garage map and detected landmarks to robustly infer the vehicle location. We also find landmark (e.g., speed bumps, turns) recognition methods reliable against noises, disturbances from bumpy rides and even hand-held movements. We implement a highly efficient prototype and conduct extensive experiments in multiple parking structures of different sizes and structures, with multiple vehicles and drivers. We find that VeTrack can estimate the vehicle's real time location with almost negligible latency, with error of 2 ∼ 4 parking spaces at 80-percentile.

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Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021

Boolean matching is significant to digital integrated circuits design. An exhaustive method for B... more Boolean matching is significant to digital integrated circuits design. An exhaustive method for Boolean matching is computationally expensive even for functions with only a few variables, because the time complexity of such an algorithm for an n-variable Boolean function is O(2 n+1 n!). Sensitivity is an important characteristic and a measure of the complexity of Boolean functions. It has been used in analysis of the complexity of algorithms in different fields. This measure could be regarded as a signature of Boolean functions and has great potential to help reduce the search space of Boolean matching. In this paper, we introduce Boolean sensitivity into Boolean matching and design several sensitivity-related signatures to enhance fast Boolean matching. First, we propose some new signatures that relate sensitivity to Boolean equivalence. Then, we prove that these signatures are prerequisites for Boolean matching, which we can use to reduce the search space of the matching problem. Besides, we develop a fast sensitivity calculation method to compute and compare these signatures of two Boolean functions. Compared with the traditional cofactor and symmetric detection methods, sensitivity is a series of signatures of another dimension. We also show that sensitivity can be easily integrated into traditional methods and distinguish the mismatched Boolean functions faster. To the best of our knowledge, this is the first work that introduces sensitivity to Boolean matching. The experimental results show that sensitivity-related signatures we proposed in this paper can reduce the search space to a very large extent, and perform up to 3x speedup over the state-of-the-art Boolean matching methods.

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An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA

ACM Transactions on Embedded Computing Systems

Transposed convolution has been prevailing in convolutional neural networks (CNNs), playing an im... more Transposed convolution has been prevailing in convolutional neural networks (CNNs), playing an important role in multiple scenarios such as image segmentation and back-propagation process of training CNNs. This mainly benefits from the ability to up-sample the input feature maps by interpolating new information from the input feature pixels. However, the backward-stencil computation constrains its performance and hindered its wide application in diverse platforms. Moreover, in contrast to the efforts on accelerating the convolution, there is a rare investigation on the acceleration of transposed convolution that is identically compute-intensive as the former. For acceleration of transposed convolution, we propose an intermediate-centric dataflow scheme, in which we decouple the generation of the intermediate patch from its further process, aiming to efficiently perform the backward-stencil computation . The intermediate-centric dataflow breaks the transposed convolution into several...

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V-PIM: An Analytical Overhead Model for Processing-in-Memory Architectures

2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA)

Processing in memory (PIM) has increasingly attracted wide interests from academy and industry wi... more Processing in memory (PIM) has increasingly attracted wide interests from academy and industry with the emergence of novel memory technologies and big-data applications. As a consequence, recent work has proposed different types of PIM architectures for various fields. However, most of their evaluations rely on dedicated simulation models, which make it hard to compare different architectures. Analytical models of PIM architectures, as a solution, have not been fully discussed in literature. To help architects and programmers easily evaluate overheads of various PIM architectures, this paper presents V-PIM, a generic and flexible analytical model. By characterizing an architecture with only several parameters, the model is simple but effective. To validate the model, we compare the results of V-PIM with simulation results against three novel PIM architectures and four tasks from data-intensive to computational-intensive. The average error of V-PIM is 15.2% or 7.1% for time or energy overheads according to our evaluation.

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Advanced Driver-Assistance Systems (ADAS) are complex systems consisting of many computer vision ... more Advanced Driver-Assistance Systems (ADAS) are complex systems consisting of many computer vision tasks including image classification, object detection and semantic segmentation. FPGA is a feasible solution for deep learning based computer vision accelerator due to its high performance and energy efficiency. However, design a high performance FPGA accelerator requires good understanding of basic hardware concepts and consumes a long compilation time. Overlays can alleviate the above problems by accelerating applications in a software via a hardware architecture and a compiler. In this paper, we propose an FPGA-based neural network overlay processor for ADAS. The overlay architecture contains almost all common computation layers for learning based ADAS. In addition, we design a compiler that can automatically compile the high-level description of neural networks from deep learning framework like Caffe and Tensorflow into FPGA configurable codes, which can be executed by our overlay architecture without reprogramming. Experiments show that our overlay can process learning tasks in ADAS with low latency and low memory usage.

SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021

Recently, the emerging resistive random access memory (RRAM) shows its potential to construct a p... more Recently, the emerging resistive random access memory (RRAM) shows its potential to construct a processing-in-memory (PIM) architecture. It supports a variety of computation modes, including the digital mode and the analog mode. Both modes can perform parallel computation inside an RRAM crossbar. However, the lack of automatic synthesis flow limits their application scenarios. Although previous works implement several large-scale applications, e.g., image processing algorithms and neural networks, using these two modes, most of their implementations are designed manually or semi-manually. In our view, the lack of a specific application representation is a limiting factor for developing a synthesis flow. Therefore, in this work, we propose the skeleton as an application representation. Users can model applications and their potential parallelism in RRAM with nested skeletons and primitive operations. Then, we propose SSR, a skeleton-based flow that can automatically synthesize large-scale applications to RRAM crossbars. For an application represented in skeletons, SSR first partitions it into the digital part and the potential analog part. After that, SSR optimizes primitive operations and allocates bounding boxes to skeletons for both parts under the guide of pre-synthesis results. Finally, SSR maps bounding boxes of skeletons onto crossbars to enable pipelined computation. Experimental evaluations on several popular applications show that SSR improves throughput, latency, and area multiple times over previous works.

Feasibility study of practical vital sign detection using millimeter-wave radios

CCF Transactions on Pervasive Computing and Interaction, Nov 15, 2021

TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021