cross-conduction in discrete driver, current-limited push/pull tristate

TLDR; capacitor C180 was added to the circuit below to make it happy.

Background: 24V PLC digital signal driver (spec: up to 15mA sourced or sunk, 100kHz, idiot proof vs shorted field wiring, able to tristate for troubleshooting by integrators). The driver IC I had been using became unavailable amid this year’s supply chain trainwreck. I thought, no problem, just throw down a few transistors.

The driver is shown below, omitting a couple of ESD/TVS protection and termination parts. SIG_VCC is the “24V” supply. The logic input comes from a 5V circuit, and in that case SIG_VBB is 2.5V. The input does level-shifting and passes on the tristate condition, or close enough for PLC purposes.

Without C180, among other things, there was cross-conduction from delayed turn-off (caused by dV/dt on the output pushing/pulling current through the output transistor’s base-collector capacitance — pretty much Miller effect). Other fixes would be to cascode, or to drive the output transistors harder, neither of which were attractive in this project. Adding C180 looks like it cleans it up reasonably well with a single component. When the inputs transition, this cap pushes/pulls current in the opposite direction from the unwanted current associated with the Miller effect. If C180 is sized right, the result is a much nicer looking trapezoidal voltage waveform on the output. (Assuming with some capacitive loading, which was ensured by some of the output-protection parts not shown.)

And here’s another convenient falstad simulation to play with, which isn’t entirely true to life, but can show the cross conduction effect going away.

LM324 op-amp oddities

This op-amp, released in 1972, is still used as an example everywhere, even though modern devices perform far better. Here are some disorganized notes on some of it’s non-ideal behaviors.

The biggest issue is the output stage. This is very well known so I won’t go into it. In the process of making measurements for the rest of this post, I did initially see the output distortion have other weird behaviors in frequency — when the output has no external load. So let’s always give this device some external load. To get it to really behave nicely, it can be biased so that it is always sourcing current. 100uA was already a massive improvement vs no load, and 1mA should be plenty. For the rest of this post I set it up with a 1K resistor to -10V, which for testing was a DC bias of around 10mA.

The middle stage of the op amp, as far as I understand, shouldn’t really be possible to manipulate by users (other than thermally). It has its own inner loop controlled by an internal compensation cap.

The input stage, unexpectedly to me, was sensitive to the resistance seen at the input terminals. The graph below summarizes – GBW starts to fall noticably after Rin>10K. At the frequencies shown, other effects like input capacitance or internal delays should be negligible.

Next, I *think* there is an internal delay. The following 3 graphs show the measurements that make me think this. The delay also seems to increase slightly vs the Rin and Rload, order of 10% change to the delay with a 10x increase in the resistances.

First, here is a calculation, of the idealized 1-term algebraic op-amp model, with GBW=1MHz, and the gain=-1 configuration — i.e. closed loop transfer function is -1/(1+2/AOL). Note the -3dB point is at half the GBW frequency.

Next here is the corresponding measurement. The feedback resistors were 1K, so their interaction with the input capacitance (several pF) should be negligible. The -3dB frequency is raised and there is quite a bit of extra phase.

Finally, here is another calculation, that expands the 1-term model to try to reproduce the above graph. A 150ns delay is added to the algebraic model. (the number was picked without any theory or measurement, just to make the graph look similar). The delay results in peaking, and raises the gain up to about where we are seeing it.

That’s it for now.

loop basics, abstract

A general SISO control loop and equivalent closed-loop transfer function expressions are shown in Figure 1. F(s) and G(s) are complex frequency domain transfer functions. Assuming they can be expressed as a ratio of polynomials, we decompose them into numerators and denominators with F = NF / DF and G = NG / DG

Figure 1

The numerators contain the zeros, and the denominators contain the poles. The expression on the rightmost side of Figure 1 then has a useful implication: We can move poles and zeros between F and G, while keeping the denominator of the closed-loop expression constant. Because the denominator is responsible for the stability of the loop, this means we can, in the abstract, keep the stability properties constant, but change how many zeros we have (including none at all).

Next, let’s break F into (H)(P), where P is our “plant”, i.e. the physical system we cannot change, and H is under our control. Typically, the controller in the forward path. This is shown in Figure 2. For the closed-loop expression, simply substitute F=HP into the Figure 1 expression..

Figure 2

The reverse path, G, is typically just an immediate sensor reading of the output. I.e. G=1. Two observations here. First, any poles added to the reverse path will create a closed-loop zero per Figure 1. This may be undesirable. Second, if our control expression has zeros, we may prefer to place them into G rather than into H, again to avoid creating closed loop zeros.

Next, let’s look at a common loop rearrangement trick. Figure 3 shows another loop configuration.

Figure 3

Here the (input-output) passing through H is mixed with the (output) passing through C, before going into plant P. We can convert between the forms in Figure 2 and Figure 3 as follows:

This can allow us to get a “free zero” without doing any differentiation, when H contains an integrator, as is common.

Most simply, if H=1/s (an integrator), and C is a constant, G = (H+C)/H = (1+Cs), i.e. a single zero. Since the equivalent G is in the reverse path, this zero will not show up in the closed loop expression.

More elaborately, if H=1/s and C=(1+s/z)/(1+s/p) , G will have two zeros and a pole at the origin. Only one zero will appear in the closed loop expression.

This can have some minor advantages when constructing single loops. In cascaded loops it can be relevant because the noise gain of the outer loop contains the closed loop gain of the inner loop. Now we have a way to remove a zero from that inner-loop’s closed loop expression (at the expense of increasing a gain elsewhere however).

fractional order lead or lag filter, approximation

Sometimes you need to tweak a control loop’s rate of closure over a frequency range. A fractional-order lead or lag filter could be used. Here are two integer-order approximations.

approximation with real-axis poles and zeros

approximation with complex-conjugate poles and zeros

The first one above, I think, would be equivalent to using the Oustaloup approximation for s𝛾 (haven’t checked this). The second one has more obscure use scenarios, where root-locus analysis may be simplified by unblocking the real axis.

Parameters:

𝛾fractional power, positive=lead, negative=lag. Slope will be (20𝛾) dB/decade
Nnumber of terms in the numerator or denominator. (2 poles/zeros per term if complex).
N is Integer >= 2
𝜔0starting frequency (radians)
𝜔fending frequency (radians)
𝜃in the expression with complex conjugate poles/zeros, angle of poles/zeros, from negative real axis

Examples (real-axis version):

term (k)zeropole
1-1.000E+00-1.000E+02
2-3.162E+01-3.162E+00
N=2, 𝛾 = 0.5 , 𝜔0 = 1, 𝜔f = 100

term (k)zeropole
1-1.000E+00-1.000E+02
2-6.813E+00-1.468E+01
3-4.642E+01-2.154E+00
N=3, 𝛾 = 0.5 , 𝜔0 = 1, 𝜔f = 100

term (k)zeropole
1-1.000E+00-1.000E+02
2-3.831E+00-2.610E+01
3-1.468E+01-6.813E+00
4-5.623E+01-1.778E+00
N=4, 𝛾 = 0.5 , 𝜔0 = 1, 𝜔f = 100

Graphs of the above examples:

another triangle, WIP

Shooting for 0.5 to 2MHz range. Haven’t built it yet.

falstad link (pictured below)

Doing this as kind-of an exercise to play around with transistors.

  • 5V single supply
  • output range 1V-3V(ish)
  • one current into resistor controls amplitude
  • another current into capacitor controls ramp rate
  • frequency is proportional to the ratio of the two currents
  • voltage level controlled by V_bot input (should be buffered coming in)
  • headroom: bottom about 1V, top is whatever the current sources require (probably diode drop + emitter resistor)

Reference: Both the 2-comparator hysteresis section, and the current-switching section, come from a Dennis Feucht book excerpt on triangle wave circuits that was published in EE times, lots of problems solved in there!

[ note to self, previous overly complicated design (falstad), included makeshift transistor buffer, just to experiment with a transistor buffer. file away somewhere else ]

weekend randomness

  • Learned about this neat sine wave circuit on Friday, apparently from the 60’s. Considered for a project later this year that’ll need a cheap 2-decade-adjustable sine wave? nah not clear that it’s better than the alternatives.
  • On Sunday night, finally got around to making a cheezy simulation of this current source, or (my original intention) like this.
    • I am hoping to fashion a two-terminal-device out of two Nagata mirrors (also from the 60’s) feeding back on each other.
    • Reference: the Nagata mirror is commonly called the “peaking current source”, and the concept has been extended by Wyatt (90s) and Hirano (2016).
    • I need to figure out how it actually works, and whether this is any better from getting gain with an emitter resistor. I also didn’t think it would self-start, but the simulation says it does.
    • A better simulation is a good idea also. Will definitely return to this.
    • To be clear, the 2-terminal application I am thinking of is totally reinventing the wheel, of the LM334 two-terminal current source, and it’s also of limited use because of the temperature coefficeint, but it’s fun.

hand soldering SMT’s

You’re looking at (1) a dentist-pick taped to a small block, and (2) another block with a loop of double-sided tape on it — the blue tape, not the green tape. We spent the development budget on tape. (click to zoom)

Place the PCB on the double-sided tape. This keeps it from moving around too much, gets the height just enough to lift up the front edge of the dentist-pick-block. Place the SMT with tweezers, hold down with the pick. Taa-dah!!! Now the hands are free to hold solder and iron!

This is quite comfortable with 0805’s (pictured). 0603’s are a balancing act, but still easier than anything that isn’t hot air.

variation on triangle wave circuit

Let’s start off with the classic 2-op-amp triangle circuit from the late 1970s. My favored variation on it, which does not seem to be well documented, is just below. Replacing R3 with a current source makes it easier to apply, in my opinion. The amplitude becomes fixed at Vpp = I1R1, the wave shape becomes independent of the level, and the level becomes adjustable. The top of the triangle output will be VIN.

Figure 1

As with the classic circuit, performance improves if the amplifier on the left is an actual comparator vs an op-amp.

I1 is probably most easily made from an LM4041 regulator, as shown at the beginning of this eariler post.

To keep the regulated current source from having to start up from scratch each time around the cycle, it can be switched, mirrored, or steered. I think steering is the best all-around option, as long as we’re not too squeezed for headroom. See below.

Figure 2

The diodes should be low-leakage and low-capacitance, such as BAS40 or BAS70. The extra diode D1 is for situations when the amplitude is small (<200mV) and the input can approach the negative rail. D1 can be omitted if this is never the case.

Click Here for a simulation!

Here is a version using bridge-steered-current to set the ramp rates.