Civil Engineering

Artificial neural networks are known to be effective in solving problems involving pattern recognition and classification. The traffic incident-detection problem can be viewed as recognizing incident patterns from incident-free patterns. A neural network classifier has to be trained first using incident and incident-free traffic data. The dimensionality of the training input data is high, and the embedded incident characteristics are not easily detectable. In this article we present a computational model for automatic traffic incident detection using discrete wavelet transform, linear discriminant analysis, and neural networks. Wavelet transform and linear discriminant analysis are used for feature extraction, denoising, and effective preprocessing of data before an adaptive neural network model is used to make the traffic incident detection. Simulated as well as actual traffic data are used to test the model. For incidents with a duration of more than 5 minutes, the incident-detection model yields a detection rate of nearly 100 percent and a false-alarm rate of about 1 percent for two-or three-lane freeways.

To eliminate false alarms, an effective traffic incident detection algorithm must be able to extract incident-related features from the traffic patterns. A robust feature-extraction algorithm also helps reduce the dimension of the input space for a neural network model without any significant loss of related traffic information, resulting in a substantial reduction in the network size, the effect of random traffic fluctuations, the number of required training samples, and the computational resources required to train the neural network. This article presents an effective traffic feature-extraction model using discrete wavelet transform (DWT) and linear discriminant analysis (LDA). The DWT is first applied to raw traffic data, and the finest resolution coefficients representing the random fluctuations of traffic are discarded. Next, LDA is employed to the filtered signal for further feature extraction and reducing the dimensionality of the problem. The results of LDA are used as input to a neural network model for traffic incident detection.

Nowadays energy consumption is a major criterion in any electronic system, especially when it comes to systems working at high throughput with restricted energy consumption constraints like in the Internet of things (IoT), wireless sensor networks, etc. In a near future, these devices will connect billions of services with different computing intensive applications including smart homes, wearable devices, health-care and smart cities. For these devices, the major source of power will be a either a battery or an energy harvesting system. In this context, new design constraints are going to appear and will definitely require to take power consumption into account during all the design process and especially in the first steps, at high-level where decisions have the greatest impact on the performances. In our work, a power estimation methodology has been proposed to allow the designer to explore various hardware architectures in terms of power consumption and performances. After a simple high-level simulation, designers are able to compare several approaches and orient their choices toward an efficient solution. In our study, FPGAs devices have been first considered but we believe that this methodology could also be applied to circuits like ASICs. This methodology consists in developing several power models for different operators or IPs like the arithmetic operators (adders, multipliers and memories), integrating them with high-level tools like Matlab and Labview for high-level power estimation. The methodology aims to make design space exploration a lot easier, providing early and fast power and performance estimation at high-level. It also proposes an efficient way to efficiently compare several systems. The methodology is effective through an operator characterization step and the development of their models. Then, a high-level description of the entire system is realized from the models that have been previously developed. High-level simulations enable to check the functionality and evaluate the power and performance of the system. These power models are based on neural networks that predict the power consumed by digital operators implemented on FPGA. These operators are interconnected and the statistical information of the data patterns are propagated among them. The obtained results make possible an overall power estimation of a specific design. A comparison is performed to evaluate the accuracy of the power models against the Xilinx Power Analyzer tool (XPA) for individual operators with an mean absolute percentage error that show an accuracy with less than 0.01%. Case studies are also presented as well as a focus on global power estimation for digital signal processing (DSP) function. Our approach shows a mean absolute percentage error of 12% versus the time consuming Xilinx classical flow of power estimation based on (XPA). This new power estimation approach based on the decomposition of a digital system into basic operators. Each operator will be given its own model which estimates the switching activity of internal and output signals. By interconnecting several operators at high-level, switching activities and percentage of logic high are then propagated to enable a global power