There is an ever demanding need to develop low power audio devices using MP3 technology. From the... more There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power. Hence to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime re-configurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and hence the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesized and simulated the architecture using 0.35 mum process technology under Synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1MHz to 20 MHz when all the multipliers are in active state.
This paper presents a selective survey of finite difference time domain (FDTD)-based interconnect... more This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving…
2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2013
In this paper a closed-form matrix rational model for the computation of step and finite ramp res... more In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Eudes method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.
In this paper, closed-form models for the computation of finite ramp responses of current-mode re... more In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring bas...
2008 International Conference on Electronic Design, 2008
LPI Radars use continuous wave, wide bandwidth low power signals of the order of a few watts maki... more LPI Radars use continuous wave, wide bandwidth low power signals of the order of a few watts making its detection difficult. The important advantage of LPI radar is to go undetected, while maintaining a strong battlefield awareness. Common spectral analysis and conventional methods fail to detect emissions of LPI radars and even normal radars in noisy environments. This leads to use higher order spectral analysis (HOSA) techniques enabling us to extract much more information from the same intercept and hence facilitating detection. This paper reports the results of HOSA techniques (bi-spectrum, bi-coherence and tri-spectrum) and artificial neural networks (ANNs), applied to LPI radar signals. Bi-phase barker coded signals of different lengths, P1, P2, P3 and P4 Polyphase coded signals and Frank signal are analyzed using HOSA techniques to produce 2-D signatures of these signals. An artificial neural network (ANN) is trained on these signatures so that it will be able to detect and i...
International Journal of Information and Communication Technology, 2009
Int. J. Information and Communication Technology, Vol. 2, Nos. 1/2, 2009 ... The effects of compi... more Int. J. Information and Communication Technology, Vol. 2, Nos. 1/2, 2009 ... The effects of compiler optimisations on embedded system power consumption ... Shuhaizar Daud*, R. Badlishah Ahmad and Nukala S. Murthy ... Embedded Computing Research Cluster, School of Computer & ...
This paper presents a selective survey of¯nite di®erence time domain (FDTD)-based interconnects m... more This paper presents a selective survey of¯nite di®erence time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modi¯cations and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the signi¯cant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.
There is an ever demanding need to develop low power audio devices using MP3 technology. From the... more There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power. Hence to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime re-configurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and hence the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesized and simulated the architecture using 0.35 mum process technology under Synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1MHz to 20 MHz when all the multipliers are in active state.
This paper presents a selective survey of finite difference time domain (FDTD)-based interconnect... more This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving…
2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2013
In this paper a closed-form matrix rational model for the computation of step and finite ramp res... more In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Eudes method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.
In this paper, closed-form models for the computation of finite ramp responses of current-mode re... more In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring bas...
2008 International Conference on Electronic Design, 2008
LPI Radars use continuous wave, wide bandwidth low power signals of the order of a few watts maki... more LPI Radars use continuous wave, wide bandwidth low power signals of the order of a few watts making its detection difficult. The important advantage of LPI radar is to go undetected, while maintaining a strong battlefield awareness. Common spectral analysis and conventional methods fail to detect emissions of LPI radars and even normal radars in noisy environments. This leads to use higher order spectral analysis (HOSA) techniques enabling us to extract much more information from the same intercept and hence facilitating detection. This paper reports the results of HOSA techniques (bi-spectrum, bi-coherence and tri-spectrum) and artificial neural networks (ANNs), applied to LPI radar signals. Bi-phase barker coded signals of different lengths, P1, P2, P3 and P4 Polyphase coded signals and Frank signal are analyzed using HOSA techniques to produce 2-D signatures of these signals. An artificial neural network (ANN) is trained on these signatures so that it will be able to detect and i...
International Journal of Information and Communication Technology, 2009
Int. J. Information and Communication Technology, Vol. 2, Nos. 1/2, 2009 ... The effects of compi... more Int. J. Information and Communication Technology, Vol. 2, Nos. 1/2, 2009 ... The effects of compiler optimisations on embedded system power consumption ... Shuhaizar Daud*, R. Badlishah Ahmad and Nukala S. Murthy ... Embedded Computing Research Cluster, School of Computer & ...
This paper presents a selective survey of¯nite di®erence time domain (FDTD)-based interconnects m... more This paper presents a selective survey of¯nite di®erence time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modi¯cations and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the signi¯cant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.
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Papers by Nukala Murthy