Papers by Vladimir M. Stojanovic
Nature, Jan 21, 2018
In this Letter, owing to an error during the production process, the author affiliations were lis... more In this Letter, owing to an error during the production process, the author affiliations were listed incorrectly. Affiliation number 5 (Colleges of Nanoscale Science and Engineering, State University of New York (SUNY)) was repeated, and affiliation numbers 6-8 were incorrect. In addition, the phrase "two oxide thickness variants" should have been "two gate oxide thickness variants". These errors have all been corrected online.
Nature, Apr 1, 2018
Electronic and photonic technologies have transformed our lives-from computing and mobile devices... more Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanc...
Public Reporting burden for Ihis collection of information is estimated to average 1 hour per res... more Public Reporting burden for Ihis collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services. Directorate for information Operations and Reports. 1215 Jefferson Davis Highway.
2007 Ieee International Conference on Communications, Jun 24, 2007
Application of Discrete Multi-tone (DMT) signaling to high-speed backplane interconnects requires... more Application of Discrete Multi-tone (DMT) signaling to high-speed backplane interconnects requires major modifications to the well-known analysis methods applied to wireline communication systems. Tight power budgets in backplane links impose severe constraints on DMT block size and use of channel shortening filters in the system. Consequently, maximum throughput is achieved in a DMT system that is (residual) interference limited and water-filling is not applicable in its original form. In this paper, the DMT system is cast as a Second Order Conic (SOC) problem with peak transmit power as the constraint and optimum integer bit-loading and power allocation are achieved through a novel incremental integer bit-loading algorithm. The convex framework is subsequently used to find "practical" upper bounds on the performance of multi-tone signaling over highspeed links. The results indicate that DMT has the potential to achieve 15-23Gbps over typical backplane channels and system requirements in terms of FFT block size and prefix length are obtained.
2015 Ieee International Symposium on Performance Analysis of Systems and Software, Mar 1, 2015
Based on voltage-to-time conversion technique, a pseudo-differential two-way-interleaved adaptive... more Based on voltage-to-time conversion technique, a pseudo-differential two-way-interleaved adaptive linear receive equalizer with two 2x-oversampled feed-forward taps has been designed in a 90 nm CMOS process. It integrates equalization and phase interpolation functions into one unit to simultaneously address inter-symbol-interference (ISI) cancellation and phase synchronization in a link receiver. It operates at 4 Gbps with 8 mW power consumption, and
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009
Tcom, 2001
Time Division Multiplexing (TDM) must be employed in multi-GSa/s transceivers in order to overcom... more Time Division Multiplexing (TDM) must be employed in multi-GSa/s transceivers in order to overcome onchip clock frequency limitations. This paper describes a transmit pre-emphasis filter for a multi-level transceiver making use of TDM. The possible applications of such a transceiver include serial links and chip-to-chip communication. The requirement of very low probability of error in the absence of coding, and the need for an adaptive solution impose a peak transmit power constraint. The TDM system is mapped to a Multiple-Input-Multiple-Output (MIMO) system, and the noise sources are analyzed. The design of the pre-emphasis filter is shown to be a non-convex optimization problem, whose optimal solution is very difficult to obtain. Still, sub-optimal solutions are derived in closed form and adaptive implementations are described. Simulation results using parameters obtained from an experimental testbed indicate that these sub-optimal solutions actually achieve very good performance.
Future single-board multi-socket systems may be unable to deliver the needed memory bandwidth ele... more Future single-board multi-socket systems may be unable to deliver the needed memory bandwidth electrically due to power limitations, which will hurt their ability to drive performance improvements. Energy efficient off-chip silicon photonics could be used to deliver the needed bandwidth, and it could be extended on-chip to create a relatively flat network topology. That flat network may make it possible to implement the same number of cores with a greater number of small dies for a cost advantage with negligible performance degradation.
... various clocked storage elements that are commonly known or used in systems with outstanding ... more ... various clocked storage elements that are commonly known or used in systems with outstanding features, such as high performance or low ... This chapter should provide the reader with a feel for the current state of the art in clocked storage elements and ... Digital System Clocking ...
This paper relates the potential energy savings to the energy profile of a circuit. These savings... more This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption subject to a delay constraint. The sensitivity of energy to delay is derived from a linear delay model extended to multiple supplies. The optimizations are applied to a range of examples that span typical circuit topologies including inverter chains, SRAM decoders and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy.
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Papers by Vladimir M. Stojanovic