Speakers
Herbert Bos
Professor, Computer Science at Vrije Universiteit Amsterdam, Netherlands
Talk : Spectre and friends: practical threats or esoteric side channel attacks?
Transient execution attacks such as Spectre, L1TF, MDS and others have occupied the security community since 2018. By now, influential members of that community have started to question the rational for this “obsession”. Are these attacks even practical? Should we not spend our research efforts on more practical threats instead, things that cause actual harm to real people? In this talk, I will consider the practicality of Spectre attacks, as well what I do and do not consider useful offensive research. To do so, I will use our attempt to compromise a real-world cloud with transient execution attacks for illustration purposes.
About the speaker
Herbert Bos is full professor at Vrije Universiteit Amsterdam where he co-leads the VUSec Systems Security group. His research interests include OS design, microarchitectural attacks and defenses, fuzzing, memory safety, automated exploitation and patching. He is very proud of his current and former students whose research results have led to five PWNIE Awards as well as changes in all major operating systems, browsers and CPUs (mostly making them slower). He is a member of the Electoral Council and the Cyber Security Council in the Netherlands. He worries about climate change, threats to democracy, and our near-total dependence on technology that is inherently insecure.
Jo Van Bulck
Professor, DistriNet Lab at KU Leuven, Belgium
Talk : The Dark Side of Privilege – Understanding and Mitigating Software-Based Side Channels on Trusted Execution Environments
Trusted Execution Environments (TEEs), enabled by recent advances in processor security, form the foundation of confidential computing in untrusted cloud infrastructure. Although privileged software such as the operating system cannot directly access TEE-protected memory, it retains control over shared hardware resources, and such control can be leveraged to launch subtle and powerful side-channel attacks. In this talk, I will examine how such software-based side channels undermine the core trust assumptions of TEEs. Drawing from our recent research, I will highlight key attack vectors, present practical mitigation strategies, and discuss broader challenges in building next-generation resilient confidential computing systems capable of withstanding the dark side of privilege.
About the speaker
Jo Van Bulck is a professor in the DistriNet lab at the Department of Computer Science of KU Leuven, Belgium. His research explores attacks and defenses at the hardware-software boundary, with particular attention to privileged side channels in trusted execution environments. Jo’s research has uncovered several innovative attack vectors in commodity Intel x86 processors that have led to microcode and silicon mitigations in hardware, as well as software patches in major operating systems and compilers.
Sylvain Guilley
CTO at Secure-IC
Talk : Embedded Cybersecurity in the Industry
This talk introduces the audience with industry tools to provide bullet-proof cybersecurity solutions. The presentation starts with the determination of validated products through a V-cycle, rooted in a risk analysis, through definition of requirements, specifications and architectures. One specificity of embedded systems is that their security covers both the manufacturing (exposed to supply chain attacks) and the mission-mode (where the users are the attackers). Documentation is key, both for adopters, certifiers, and developers: we’ll describe the corpus required by Common Criteria methodology. Well maintained security improves, hence maturity shall be measured (by TRL) and developed. Eventually, remaining gaps can be bridged by ecosystem coordination, using tools such as standards or regulations. This presentation is illustrated on the example of chiplets’ open market.
About the speaker
Sylvain Guilley is Fellow at Cadence Design Systems, and invited professor at Télécom Paris. Sylvain previously co-founded Secure-IC, now integrated within Cadence. Sylvain holds an HDR (accreditation to supervise research) from Paris 7 University (2011), a PhD from Télécom Paris (2007), and is alumnus from Ecole Polytechnique (X 1997). Sylvain is also research associate at Ecole Normale Superieure (ENS).
He is lead editor of international standards, such as ISO/IEC 20897 (Physically Unclonable Functions), ISO/IEC 20085 (Calibration of non-invasive testing tools), and ISO/IEC TR 24485 (White Box Cryptography).
As administrator of Embedded France professional association, he leads the cybersecurity working group. Sylvain has co-authored 350+ research papers and filed 40+ invention patents. He is member of the IACR, senior member of the IEEE and the CryptArchi club.
Daniel Gruss
Professor, Computer Science at Graz University of Technology
Talk : Attacks on Microarchitectures in Software and Hardware
In this talk, we will learn how both software and hardware have a kind of “microarchitecture” that introduces effects like timing differences. These effects can be exploited in side-channel attacks. We will look at several such attacks and see what an attacker can leak and how these attacks can be mitigated. In the hands-on part, we will mount side-channel attacks to find leakage in real-world applications.
About the speaker
Daniel Gruss is a university professor in the Secure Systems group (Team Gruss/CoreSec) at the Graz University of Technology, Institute of Applied Information Processing and Communications. His research focuses on software-based microarchitectural attacks and operating system features. He teaches undergraduate courses including Operating Systems, System-Level Programming, Information Security, and Introduction to Scientific Working, and, together with his PhD students, graduate courses such as Side Channel Security, Secure Software Development, and Cloud Operating Systems.
Boris Köpf
Principal Researcher at Azure Research, Cambridge, UK
Talk : Information-flow tracking at the hardware-software interface
Speculative execution attacks such as Spectre and Meltdown exploit microarchitectural optimizations to leak information across security domains. In this lecture, we will study speculative execution attacks through the lens of Formal Methods. We will start with a tutorial on the basics of information-flow analysis and use these concepts to augment the hardware-software contract to account for speculative leaks. We will then discuss how to use such contracts to detect unknown leaks in software and hardware (the basis for the session on Revizor), and how to build secure systems by composition.
About the speaker
Boris Köpf is a scientist at Azure Research (formerly the Confidential Computing group at Microsoft Research), where he works on techniques for tracking information flow in microarchitectures and machine learning systems. Before joining Microsoft in November 2018, he was a tenured faculty member at the IMDEA Software Institute, a postdoctoral researcher at the Max Planck Institute for Software Systems, and completed his Ph.D. at ETH Zurich.
Onur Mutlu
Professor, Computer Science at ETH Zurich, Switzerland
Talk : RowHammer, RowPress and Beyond: Fantastic Bitflips and Where to Find Them
We will examine the RowHammer problem in Dynamic Random Access Memory (DRAM), the first example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. RowHammer is the phenomenon that repeatedly accessing a row in a modern DRAM chip predictably causes bitflips in physically-adjacent rows. Building on our initial fundamental work that appeared at ISCA 2014, Google Project Zero demonstrated that this hardware phenomenon can be exploited by user-level programs to gain kernel privileges. Many other works demonstrated other attacks exploiting RowHammer, including remote takeover of a server vulnerable to RowHammer, takeover of a mobile device by a malicious user-level application, and destruction of predictive capabilities of commonly-used deep neural networks.
Unfortunately, the RowHammer problem and other read disturbance issues continue to plague cutting-edge DRAM chips, DDR4, DDR5, HBMx and beyond. Based on our extensive characterization studies of more than 1500 real DRAM chips from six technology generations that appeared at ISCA 2020 and MICRO 2021, we show that RowHammer at the circuit level is getting much worse, newer DRAM chips are much more vulnerable to RowHammer than older ones, and existing mitigation techniques do not work well. We also show that proprietary mitigation techniques employed in DDR4 DRAM chips, which were advertised to be Rowhammer-free, can be bypassed via many-sided hammering (also known as TRRespass (IEEE S&P 2020) & Uncovering TRR, (MICRO 2021)). At ISCA 2023, we demonstrated the RowPress problem, which is a different type of read disturbance vulnerability in DRAM that also affects all recent DRAM chips. RowPress greatly (e.g., by 100X) reduces the activation count required to induce bitflips, by keeping an activated row open for a long time. Multiple works have already replicated and exploited the RowPress problem. Using our extensive DRAM testing infrastructure, we recently discovered various other read disturbance bitflip phenomena in real DRAM chips, including PUDHammer (ISCA 2025), Variable Read Disturbance (HPCA 2025), and ColumnDisturb (MICRO 2025). We believe there are a lot more fascinating discoveries to come in finding bitflip sources in DRAM (and solving them), as DRAM technology continues to scale to ever-smaller technology node sizes to feed the ever-increasing memory capacity demands.
In this talk, we will provide an overview of RowHammer, RowPress, ColumnDisturb and other cutting-edge DRAM read disturbance research & developments in academia and industry, with a special focus on recent works that rigorously analyze real chip characteristics and introduce promising solution ideas. We will discuss the effect of such bit flips especially on DDR4 and High-Bandwidth Memory (HBM) chips, which form the foundations of modern AI infrastructures. We will also discuss what other problems may be lurking in DRAM and other types of memory, which can potentially threaten the foundations of reliable and secure systems, as memory technologies scale to higher densities. We will conclude by describing and advocating a principled approach to memory robustness (including security, reliability, safety, availability) research that can enable us to better anticipate and prevent such vulnerabilities.
A short accompanying paper, which appeared at ASP-DAC 2023, can be found here and serves as recommended reading:
“Fundamentally Understanding and Solving RowHammer”
https://arxiv.org/abs/2211.07613
A longer paper that provides an overview of the RowHammer problem and research, which appeared at IEEE TCAD 2019, can be found here and serves as recommended reading:
“RowHammer: A Retrospective”
https://arxiv.org/pdf/1904.09724
About the speaker
Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. Many techniques he, with his group and collaborators, has invented over the years have largely influenced industry and have been employed in commercial microprocessors and memory & storage systems used daily by billions of people. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his impactful research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems,” 2024 IFIP Jean-Claude Laprie Award in Dependable Computing (for the original RowHammer work), 2021 IEEE High Performance Computer Architecture Conference Test of Time Award (for the Runahead Execution work), 2022 Persistent Impact Prize of the Non-Volatile Memory Systems Workshop (for the original architectural work on Phase Change Memory), 2025 IEEE/IFIP International Conference on Dependable Systems and Networks Test-of-Time Award (for the AVATAR work), 2023 Huawei OlympusMons Award in Storage Systems, 2021 Intel Outstanding Researcher Award, 2019 ACM SIGARCH Maurice Wilkes Award, and dozens of best paper, “Top Pick” paper, and Best Artifact recognitions at various leading computer systems, architecture, and security venues. He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 25 PhD graduates, many of whom received major dissertation & other awards, 18 postdoctoral trainees, and more than 70 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube (https://www.youtube.com/OnurMutluLectures & https://www.youtube.com/@CMUCompArch), and his research group (https://safari.ethz.ch/) makes a wide variety of open-source artifacts freely available online (https://github.com/CMU-SAFARI). For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.
Oleksii Oleksenko
Senior Researcher at Azure Research, Cambridge, UK
Talk : Revizor as a Platform for Side Channel Testing
This session will demonstrate how to use Revizor to systematically test commercial CPUs for microarchitectural security vulnerabilities. Participants will learn to how to configure Revizor for detection of previously unknown microarchitectural leaks, how to execute a fuzzing campaign, and how to analyse results to identify root causes. Through practical examples on real hardware, attendees will gain experience with hardware-software contract testing and vulnerability triage techniques for speculative information leaks.
About the speaker
Oleksii is a senior researcher at Azure Research, Microsoft in Cambridge, UK. His main focus is on microarchitectural/side-channel vulnerabilities, such as Spectre and Meltdown. He develops specs to describe them, builds tools that detect them, and develops mitigations against these vulnerabilities, across multiple layers of the computing stack
Olivier Rioul
Professor at the Department of Communication and Electronics at Télécom Paris, Institut Polytechnique de Paris, France
Talk : How can alpha-information theory formally prove that your sensitive circuits are protected against side-channel attacks?
Side-channel attacks exploit sensitive information leaks to recover the secret in a “divide and conquer” approach. From an information theoretic point of view, the question is not whether you are secure or not, since it is only a matter of time. The question is how much you can be secure, e.g. with a protected implementation that use data masking. For that, we need a formal evaluation.
In this talk, I present such a formal evaluation using alpha-information theory, based on Rényi alpha-divergence and alpha-entropy, and Sibson’s alpha-information. The parameter alpha can be positive or negative, and the limiting case alpha = minus infinity is related to the important notion of Doeblin coefficient, which can be used to reduce the noisy leakage model to a random probing model. Fano and data processing inequalities, as well as Mrs. Gerber’s lemma in the case of additive masking, are used to establish lower bounds on the number of queries that any attacker has to make to achieve a given level of success. In this way, it is possible to be proactive to maintain the security of an implementation.
About the speaker
Olivier Rioul (https://perso.telecom-paristech.fr/rioul/) is full Professor at the Department of Communication and Electronics at Télécom Paris, Institut Polytechnique de Paris, France. He graduated from École Polytechnique and from École Nationale Supérieure des Télécommunications, Paris, France, where he obtained his PhD degree. His research interests are in applied mathematics and include various, sometimes unconventional, applications of information theory such as inequalities in statistics, hardware security, and experimental psychology. He has been teaching information theory and statistics at various universities for twenty years and has published a textbook which has become a classical French reference in the field.
Michael Schwarz
Senior Researcher, CISPA Helmholtz Center for Information Security, Germany
Talk : RISC-V: Curse or Blessing for CPU Security? The Open-Source Dream Meets Microarchitectural Reality
RISC-V was meant to fix everything: no black boxes, no vendor secrets, just clean, open hardware for a secure future. At least, that was the dream. Reality, however, looks messier. In this talk, we trace how openness meets microarchitectural chaos. Where even the simplest RISC-V cores stumble over side channels, denial-of-service bugs, and privilege escalations that feel straight out of the x86 playbook. Drawing on a decade of breaking CPUs (Spectre, Meltdown, and friends), we question whether RISC-V is truly the security fresh start it could have been, or just another chapter in the same cat-and-mouse story. Only this time, the mouse brought its own open-source trap. Along the way, we look at why CPU testing still lags far behind software testing, why “open” doesn’t mean “secure”, and what the future of trustworthy CPUs could look like.
About the speaker
Dr. Michael Schwarz is tenured faculty at CISPA with a focus on microarchitectural side-channel attacks and system security. He obtained his PhD with the title “Software-based Side-Channel Attacks and Defenses in Restricted Environments” in 2019 from Graz University of Technology (advised by Daniel Gruss). He holds two master’s degrees, one in computer science and one in software engineering with a strong focus on security. Michael is a regular speaker at both academic and hacker conferences (7 times Black Hat, CCC, Blue Hat, etc.). He was part of one of the research teams that found the Meltdown, Spectre, Fallout, and LVI vulnerabilities, as well as the ZombieLoad vulnerability. He was also part of the KAISER patch, the basis for Meltdown countermeasures now deployed in every modern operating system under names such as KPTI or KVA Shadow.
Shweta Shinde
Assistant Professor, Computer Science at ETH Zurich, Switzerland
Talk : Confidential Computing in Three Acts
This talk will begin with the foundations of confidential computing, tracing its origins from early research to hardware support for trusted execution environments. We will explore where earlier platforms faced challenges, while Intel SGX marked a pivotal moment in defining and democratizing confidential computing. The second act will focus on the shift from enclaves to confidential virtual machines, and how we are revisiting a similar cycle of attacks and defenses, this time with an untrusted hypervisor. Finally, we will look toward a hopeful future, examining the potential of confidential computing in enabling innovative use cases, such as sovereign smartphones, and its expanding role in accelerators and custom silicon for large-scale data centers.
About the speaker
Shweta Shinde is an assistant professor in the Department of Computer Science at ETH Zurich, where she leads the Secure & Trustworthy Systems (SECTRS) research group. She is a member of both the Institute of Information Security and the Zurich Information Security and Privacy Center (ZISC).
Her research focuses on the intersection of trusted computing, system security, and program analysis. Together with her group, she explores both the theoretical foundations and practical implementations of security, aiming to protect systems ranging from mobile phones and servers to specialized accelerators by designing and building secure, large-scale systems.
Francois Xavier Standaert
Research Director (FNRS-F.R.S), Professor at UCLouvain, Belgium
Talk : Side-channel analysis and leakage-resistance (trying to structure two decades of research)
Physical side-channel attacks exploiting the power consumption or electromagnetic radiation of cryptographic implementations have been and still are a topic of intense research, both on the evaluation and on the design fronts. In this talk, I will (try to) motivate and introduce efforts towards systematizing the lessons learned from two decades of research into design and evaluation guidelines that lead to strong physical security guarantees. Besides the (quite inter-disciplinary) technical tools that must be used for this purpose, I will also argue that, as in the standard cryptographic setting, such strong security guarantees require proper definitions of the goals together with a good separation of duties between falsifiable (physical) assumptions and their mathematical amplification. As in the standard cryptographic setting (and in many places in security), it is in turn calling for open source implementations.
About the speaker
François-Xavier Standaert is a professor at UCLouvain and research director at the Belgian Fund for Scientific Research (FNRS-F.R.S.). He received his PhD in Electrical Engineering from UCLouvain in 2004. He was a Fulbright visiting researcher at Columbia University and MIT in 2004–2005, and a founding member of IntoPix s.a. in 2006. His research focuses on cryptographic hardware, embedded systems, and physical security, including side-channel and fault attacks. He has received multiple European Research Council (ERC) grants—Starting (2011), Consolidator (2016), and Advanced (2023)—and was elevated to IACR Fellow in 2024.
Ingrid Verbauwhede
Professor, COSIC Research Group at KU Leuven, Belgium
Talk: Practical Memory Aliasing Attacks on Trusted Execution Environments – Co-presented with Jesse De Meulemeester
Trusted Execution Environments (TEEs) such as AMD SEV-SNP, Intel SGX, and Intel TDX are critical to securing sensitive data in cloud computing, promising protections even against hardware attackers. However, recent scalable designs have loosened the robustness of their memory encryption to support larger protected memory sizes. These reduced guarantees necessitate strong access control to prevent vulnerabilities stemming from the static encryption. Our research has shown that an incorrect memory controller configuration could bypass these checks, re-enabling these attacks.
In this talk, we will present BadRAM, a novel attack that exploits the memory initialization by modifying the Serial Presence Detect (SPD) chip in common DDR4 and DDR5 memory modules. Using a low-cost, practical setup, we show how the memory controller can be tricked into creating ghost memory regions that alias with protected ranges. We then demonstrate how this memory aliasing can bypass TEE protections, leading to critical vulnerabilities in AMD SEV-SNP, including the ability to corrupt or replay ciphertext, and even fully compromise their attestation feature.
We will also explore the broader impact of memory aliasing on other TEEs, including write-pattern leakage in classical SGX and the robust countermeasures deployed by Scalable SGX and TDX. Finally, we will discuss mitigations, such as alias checking and the adoption of cryptographically strong memory protection, and compare the currentmitigations in SEV-SNP, Scalable SGX, and TDX. In this talk, we will
highlight the critical need for robust defenses against physical and software-level attacks on DRAM, as well as reevaluate trust assumptions in scalable TEE designs.
About the speaker
Dr. Ingrid Verbauwhede is a professor in the COSIC research group at the Department of Electrical Engineering, KU Leuven, where she leads the embedded systems and hardware team. She is also an adjunct professor at UCLA’s Department of Electrical Engineering. She joined KU Leuven in 2003 and UCLA in 1998, following earlier roles at UC Berkeley, TCSI, and Atmel Lab. She is a Fellow of the IEEE, a member of the IACR, and was elected to the Royal Flemish Academy of Belgium for Science and the Arts in 2011. In 2016, she received a European Research Council (ERC) Advanced Grant. A pioneer in the secure and efficient design of cryptographic algorithms for embedded systems, Dr. Verbauwhede has contributed extensively to hardware and software co-design for symmetric, public key, and post-quantum cryptography. Her work spans ASICs, FPGAs, and embedded software, with a focus on side-channel resistance, secure random number generation, physically unclonable functions, and attack-resistant circuit design.
Jesse De Meulemeester
PhD candidate, COSIC Research Group at KU Leuven, Belgium
Talk: Practical Memory Aliasing Attacks on Trusted Execution Environments – Co-presented with Ingrid Verbauwhede
About the speaker
Jesse De Meulemeester is a PhD candidate at the COSIC research group, where he is part of the hardware security division, supervised by Professor Ingrid Verbauwhede. His main interests are physical attacks and defenses on high-end systems. His research focuses on the intersection of physical and micro-architectural attacks. He is supported by an FWO fellowship, evaluating the security of modern devices, and contributing to secure open-source and open-specification hardware and software for next-generation devices.
Yuval Yarom
Professor, Computer Science at Ruhr University Bochum (RUB), Germany
Talk: Emergent Behavior and Weird Machines in CPUs
Over the last decades computers have become incredibly complex. Modern computers are an intricate combination of hundreds of microarchitectural components, such as caches, execution engines, and various predictors. These all are orchestrated to achieve the ever increasing performance we expect as the field advances. Like in many complex systems, the complexity of microarchitectural components of modern computers and their interaction gives rise to emergent behavior that was not anticipated from the design. This emergent behavior is the topic of this talk. We focus at first on cache state, demonstrating that it is complex enough to allow arbitrary computation. The main mechanism we use is weird gates, which are software constructs whose execution performs logical functions on cache state. We then discuss some uses of such weird gate, and conclude with discussing how more advanced constructions can be realized.
About the speaker
From April 2023, he has been a Professor of Computer Science at Ruhr University Bochum (RUB). Before joining RUB, he was an Associate Professor at the School of Computer and Mathematical Sciences at the University of Adelaide. He earned his Ph.D. in Computer Science from the University of Adelaide in 2014, and his M.Sc. in Computer Science and B.Sc. in Mathematics and Computer Science from the Hebrew University of Jerusalem in 1993 and 1990, respectively. In between, he served as the Vice President of Research at Memco Software and was a co-founder and Chief Technology Officer of Girafa.com.
His research explores the security of the interface between software and hardware. In particular, he is interested in the discrepancy between the way programmers perceive software execution and its actual execution in modern processors. His work focuses on identifying micro-architectural vulnerabilities, as well as developing exploitation and mitigation techniques.