Papers by Richa Parihar CF
The MOSFET device performance deteriorates when it is scaled down to 45nm node and an alternative... more The MOSFET device performance deteriorates when it is scaled down to 45nm node and an alternative device structure being studied. FinFETs are the alternative new device structure, which replaces the MOSFET. The comparative study of Double Gate MOSFET (DGMOSFET), Tri-gate Fin Field Effect Transistor (FinFET) and Gate All Around (GAA) FinFET structures has been done for 22nm and 16nm technologies. The study is based on the ground of logic performance parameters which are I on /I off current ratio, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold voltage (V t) roll-off. These parameters are also termed as Short Channel Effects (SCEs) and for a nanoscale device performance these parameters needs to be controlled. The parameters are evaluated for various high-k dielectric materials. The high-κ dielectric Hafnium oxide (HfO 2) exhibits the best material to minimize SCEs for GAA structures. The aforementioned devices are also tested for transconductance (g m) which is an analog performance parameter. The accuracy of the results has been verified by 3-D SILVACO ATLAS. Keywords-Drain Induced Barrier Lowering (DIBL), double gate MOSFET (DGMOSFET), Fin Field Effect Transistor (FinFET) and Gate All Around (GAA), Ion/Ioff ratio, Subthreshold Swing (SS), Transconductance (g m).
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Papers by Richa Parihar CF