In this paper, an embedded system for motion control of omnidirectional mobile robots is presente... more In this paper, an embedded system for motion control of omnidirectional mobile robots is presented. An omnidirectional mobile robot is a type of holonomic robots. It can move simultaneously and independently in translation and rotation. The RoboCup small-size league, a robotic soccer competition, is chosen as the research platform in this paper. The first part of this research is to design and implement an embedded system that can communicate with a remote server using a wireless link, and execute received commands. Second, a fuzzy-tuned proportional-integral (PI) path planner and a related low-level controller are proposed to attain optimal input for driving a linear discrete dynamic model of the omnidirectional mobile robot. To fit the planning requirements and avoid slippage, velocity, and acceleration filters are also employed. In particular, low-level optimal controllers, such as a linear quadratic regulator (LQR) for multiple-input-multiple-output acceleration and deceleration of velocity are investigated, where an LQR controller is running on the robot with feedback from motor encoders or sensors. Simultaneously, a fuzzy adaptive PI is used as a highlevel controller for position monitoring, where an appropriate vision system is used as a source of position feedback. A key contribution presented in this research is an improvement in the combined fuzzy-PI LQR controller over a traditional PI controller. Moreover, the efficiency of the proposed approach and PI controller are also discussed. Simulation and experimental evaluations are conducted with and without external disturbance. An optimal result to decrease the variances between the target trajectory and the actual output is delivered by the onboard regulator controller in this paper. The modeling and experimental results confirm the claim that utilizing the new approach in trajectory-planning controllers results in more precise motion of four-wheeled omnidirectional mobile robots.
A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. I... more A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. In essence, each sensor node is a small form-factor, potentially miniature, batterypowered device, comprising processing, memory, RF transceiver, and sensing modules. Facilitating remote interaction with the physical world, wireless sensor networks are becoming increasingly ubiquitous. Demanding diverse service and performance requirements, environmental, agricultural, industrial, consumer, automotive, healthcare, and military applications utilize such networks. In addition, microscopic, and subsequent nanoscopic, wireless sensor networks are envisaged in the future, with positive ramifications for numerous fields and disciplines. In this paper, we comprehensively study the performance of autonomous wireless sensor networks. The paper considers randomized, contention-free, and hybrid medium access technologies. Specifically, it investigates the performance of IEEE 802.15.4 slotted CSMA-CA, IEEE 802.15.4 unslotted CSMA-CA, IEEE 802.11 DCF, S-MAC, and dGTS. Unlike existing analytical and simulation studies, we consider multi-hop connectivity, and accurately emulate link-layer interactions as well as examine the end-to-end performance in the presence of static and dynamic routing. For below-saturation offered loads, the simulations reveal that dGTS achieves 100% delivery ratios and outperforms the other technologies with respect to the throughput, often by a remarkable margin. The majority of the simulation scenarios show the IEEE 802.11 DCF surpassing the IEEE 802.15.4 CSMA-CA variants, a result attributed to the former's medium reservation mechanism. At the expense of its network performance, S-MAC dissipates the least amount of energy. For instance, regardless of the routing method and offered load used, its throughput does not exceed 5% of the channel capacity. From a power-awareness standpoint, dGTS ranks second to S-MAC when dynamic routing is employed. Leveraging the complementary features of randomized and contention-free schemes, dGTS provides a robust and powerefficient solution for wireless sensor networks.
The objective of this research is to design an efficient and flexible implementation of parallel ... more The objective of this research is to design an efficient and flexible implementation of parallel matrix multiplication for FPGA devices by analyzing the computation and studying its design space. In order to adapt to the FPGA platform, the design employs blocking and parallelization. Blocked matrix multiplication enables processing arbitrarily large matrices using limited memory capacity, and reduces the bandwidth requirements across the device boundaries by reusing available elements. Exploiting the inherent parallelism in the matrix multiplication computation improves the performance and utilizes the available reconfigurable FPGA resources. The design is constructed by identifying the main design decisions and evaluating the alternatives for each one. The considered design decisions include the scheduling of block transfers, the scheduling of arithmetic operations in a block multiplication, the extent to which the parallelism is exploited, determining the block sizes and shapes, and the use of double buffers for storing matrix blocks. The choices offered by each decision are evaluated analytically in terms of their performance and utilization of FPGA resources. Based on this analysis, a detailed, flexible design that accommodates various alternative design choices is described. The design is optimized for matrices of floating-point elements, and for the FPGA target platform. Prior work is analyzed based on the considered design choices in order to identify the similarities and the differences. The proposed design is implemented using the VHDL hardware description language. The implementation is used to verify the correctness of the design and to confirm the analysis of the design decisions. Correctness is verified both by simulation using the ModelSim i Abstract logic simulator, and in hardware through compiling the implementation using the Altera Quartus II CAD software and testing it on the Altera DE4 board, featuring a Stratix IV EP4SGX530C2 FPGA device. The implementation supports a range of parameters to facilitate the experimental evaluation of design choices. Experimental results show that the design scales linearly with respect to the consumed resources. Although increasing the system size reduces the maximum operating frequency, it also increases the parallelism, resulting in a higher performance. For instance, with 8 floating-point arithmetic units, the system runs at 320 MHz, which corresponds to a performance of 4 GFLOPS, whereas with 64 arithmetic units, it runs at 160 MHz, which corresponds to a performance of 16 GFLOPS. It is also shown that using a transfer schedule based on inner products reduces the transfer time by up to 50% compared to other schedules. Although using square blocks minimizes the number of required block multiplications, other non-square blocks minimize the transfer time, resulting in better total times. I would like to express my gratitude to my supervisor, Dr. Naraig Manjikian, for his continuous guidance and valuable insight, and for his generosity with his time. I am inspired by his dedication to providing effective education and by his attention to detail. I would like to thank my wife, Arwa, and our children, Yazeed, Sahar, and our newest addition, Jana, for their patience and their support, and for the sacrifices they had to make. I am also thankful to my parents for their inspiration and encouragement, and for teaching me to be a lifelong student and seeker of knowledge. I would like to thank King Fahd University of Petroleum & Minerals in Dhahran, Saudi Arabia, for providing the funding for my graduate studies. Hardware and software support for pursuing the implementation effort in this research was provided by CMC Microsystems and Altera Corporation.
A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. I... more A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. In essence, each sensor node is a small form-factor, potentially miniature, battery-powered device, comprising processing, memory, RF transceiver, and sensing modules. Facilitating remote interaction with the physical world, wireless sensor networks are becoming increas-ingly ubiquitous. Demanding diverse service and performance requirements, environmental, agricultural, industrial, consumer, automotive, healthcare, and military applications utilize such networks. In addition, microscopic, and subsequent nanoscopic, wireless sensor networks are envisaged in the future, with positive ramifications for numerous fields and disciplines. In this paper, we comprehensively study the performance of autonomous wireless sensor networks. The paper considers randomized, contention-free, and hybrid medium access technologies. Specif-ically, it investigates the performance of IEEE 802.15.4 slotted CSMA...
ABSTRACT This paper describes performance optimizations of a transfer controller for an FPGA-base... more ABSTRACT This paper describes performance optimizations of a transfer controller for an FPGA-based blocked parallel matrix multiplication accelerator. One of the key challenges of the controller is the generation of a sequence of host memory addresses to transfer blocks of matrices between host and on-chip memories. These addresses are not contiguous, thereby introducing complexity for the controller design. This paper first outlines the intended system architecture for this controller. Next, detailed controller specifications are presented for generating host memory addresses. Various pipeline configurations that yield incremental performance improvements are then described. Finally, experimental results are presented, with the best configuration having an operating frequency exceeding 470 MHz on an Altera Stratix III chip. This level of performance is comparable to that of the pipelined floating-point arithmetic units in the complete system.
Abstract FPGA technology constitutes an attractive platform for high-performance accelerators of ... more Abstract FPGA technology constitutes an attractive platform for high-performance accelerators of parallel workloads in general-purpose computers. Matrix multiplication is a computationally intensive application that is highly parallelizable. Previous work has ...
IEEE 802.15.4 is a low-power, low-rate MAC/PHY standard that meets most of the stringent requirem... more IEEE 802.15.4 is a low-power, low-rate MAC/PHY standard that meets most of the stringent requirements of singlehop wireless sensor networks. Sensor networks with nodal populations composed of thousands of devices have been envisioned in conjunction with environmental, vehicular, military applications, and many others. However, such large sensor network deployments necessitate multihop support as well as low power consumption. In the light of the standard's extremely limited joint support of the two aforementioned attributes, this paper presents two essential contributions. First, a framework is proposed to implement a new IEEE 802.15.4 operating mode, namely, the synchronized peer-to-peer mode. This mode is designed to enable the standard's low-power features in peer-to-peer multihop-ready topologies. The second contribution is a distributed GTS (dGTS) management scheme designed to function in the newly devised network mode. This protocol provides reliable contention-free access in peer-topeer topologies in a completely distributed manner. Assuming optimal routing, our simulation experiments reveal perfect delivery ratios as long as the traffic load does not reach or surpass its saturation threshold. dGTS sustains at least twice the delivery ratio of contention-based access under suboptimal dynamic routing. Moreover, the dGTS scheme exhibits minimum power consumption by eliminating the retransmissions attributed to contention, which, in turn, reduces the number of transmissions to a minimum.
Canadian Journal of Electrical and Computer Engineering, 2014
This paper considers blocking and scheduling for the design and implementation of field-programma... more This paper considers blocking and scheduling for the design and implementation of field-programmable gate array (FPGA)-based floating-point parallel matrix multiplication in the presence of a memory hierarchy. For high performance, on-chip memory holds data that are reused when the computation is divided into blocks, and multiple arithmetic units perform independent operations within each block in parallel. The first contribution of this paper is a detailed analysis of the design space to characterize performance based on the amount of on-chip memory used and the approaches considered for blocking and scheduling of the computation. A comparison is also made to prior work with a unified view. The second contribution is a flexible high-performance implementation for the Altera Stratix IV EP4SGX530C2 FPGA with an interface to external double-data-rate synchronous dynamic RAM DDR2 SDRAM) memory. Various configuration options support optimization of different objectives, and the resulting configurations have been verified in simulation and in hardware. For double-precision floating-point, a performance of 16 giga-floating-point operations per second (GFLOPS) is achievable with 64 arithmetic units at 160 MHz. Résumé-Cet article traite le blocage et la planification pour la conception et l'implémentation d'une multiplication matricielle parallèle à virgule flottante en utilisant un circuit logique programmable (FPGA) avec une hiérarchie de mémoire. Pour atteindre des hautes performances, une mémoire sur puce contient des données qui sont réutilisées lorsque le calcul est divisé en sous blocs, et plusieurs unités arithmétiques réalisent des opérations indépendantes dans chaque bloc en parallèle. La première contribution de cet article est une analyse détaillée de l'espace de conception pour caractériser la performance basée sur la quantité de mémoire sur puce utilisée et les approches envisagées pour le blocage et l'ordonnancement du calcul. Une comparaison normalisée est également présentée par rapport à des travaux antérieurs. La seconde contribution est une implémentation haute performance et flexible sur un FPGA Altera Stratix IV EP4SGX530C2 avec une interface pour une mémoire externe synchrone et dynamique à double débit de données (DDR2 SDRAM). Plusieurs options de configuration pour optimiser différents objectifs, et des configurations subséquentes ont été vérifiées par des simulations ainsi que par implémentation. Pour doubler la précision en virgule flottante, une performance de 16 opérations de giga-virgule flottante par seconde (GFLOPS) est réalisée avec 64 unités arithmétiques à 160 MHz.
In this paper, an embedded system for motion control of omnidirectional mobile robots is presente... more In this paper, an embedded system for motion control of omnidirectional mobile robots is presented. An omnidirectional mobile robot is a type of holonomic robots. It can move simultaneously and independently in translation and rotation. The RoboCup small-size league, a robotic soccer competition, is chosen as the research platform in this paper. The first part of this research is to design and implement an embedded system that can communicate with a remote server using a wireless link, and execute received commands. Second, a fuzzy-tuned proportional-integral (PI) path planner and a related low-level controller are proposed to attain optimal input for driving a linear discrete dynamic model of the omnidirectional mobile robot. To fit the planning requirements and avoid slippage, velocity, and acceleration filters are also employed. In particular, low-level optimal controllers, such as a linear quadratic regulator (LQR) for multiple-input-multiple-output acceleration and deceleration of velocity are investigated, where an LQR controller is running on the robot with feedback from motor encoders or sensors. Simultaneously, a fuzzy adaptive PI is used as a highlevel controller for position monitoring, where an appropriate vision system is used as a source of position feedback. A key contribution presented in this research is an improvement in the combined fuzzy-PI LQR controller over a traditional PI controller. Moreover, the efficiency of the proposed approach and PI controller are also discussed. Simulation and experimental evaluations are conducted with and without external disturbance. An optimal result to decrease the variances between the target trajectory and the actual output is delivered by the onboard regulator controller in this paper. The modeling and experimental results confirm the claim that utilizing the new approach in trajectory-planning controllers results in more precise motion of four-wheeled omnidirectional mobile robots.
A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. I... more A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. In essence, each sensor node is a small form-factor, potentially miniature, batterypowered device, comprising processing, memory, RF transceiver, and sensing modules. Facilitating remote interaction with the physical world, wireless sensor networks are becoming increasingly ubiquitous. Demanding diverse service and performance requirements, environmental, agricultural, industrial, consumer, automotive, healthcare, and military applications utilize such networks. In addition, microscopic, and subsequent nanoscopic, wireless sensor networks are envisaged in the future, with positive ramifications for numerous fields and disciplines. In this paper, we comprehensively study the performance of autonomous wireless sensor networks. The paper considers randomized, contention-free, and hybrid medium access technologies. Specifically, it investigates the performance of IEEE 802.15.4 slotted CSMA-CA, IEEE 802.15.4 unslotted CSMA-CA, IEEE 802.11 DCF, S-MAC, and dGTS. Unlike existing analytical and simulation studies, we consider multi-hop connectivity, and accurately emulate link-layer interactions as well as examine the end-to-end performance in the presence of static and dynamic routing. For below-saturation offered loads, the simulations reveal that dGTS achieves 100% delivery ratios and outperforms the other technologies with respect to the throughput, often by a remarkable margin. The majority of the simulation scenarios show the IEEE 802.11 DCF surpassing the IEEE 802.15.4 CSMA-CA variants, a result attributed to the former's medium reservation mechanism. At the expense of its network performance, S-MAC dissipates the least amount of energy. For instance, regardless of the routing method and offered load used, its throughput does not exceed 5% of the channel capacity. From a power-awareness standpoint, dGTS ranks second to S-MAC when dynamic routing is employed. Leveraging the complementary features of randomized and contention-free schemes, dGTS provides a robust and powerefficient solution for wireless sensor networks.
The objective of this research is to design an efficient and flexible implementation of parallel ... more The objective of this research is to design an efficient and flexible implementation of parallel matrix multiplication for FPGA devices by analyzing the computation and studying its design space. In order to adapt to the FPGA platform, the design employs blocking and parallelization. Blocked matrix multiplication enables processing arbitrarily large matrices using limited memory capacity, and reduces the bandwidth requirements across the device boundaries by reusing available elements. Exploiting the inherent parallelism in the matrix multiplication computation improves the performance and utilizes the available reconfigurable FPGA resources. The design is constructed by identifying the main design decisions and evaluating the alternatives for each one. The considered design decisions include the scheduling of block transfers, the scheduling of arithmetic operations in a block multiplication, the extent to which the parallelism is exploited, determining the block sizes and shapes, and the use of double buffers for storing matrix blocks. The choices offered by each decision are evaluated analytically in terms of their performance and utilization of FPGA resources. Based on this analysis, a detailed, flexible design that accommodates various alternative design choices is described. The design is optimized for matrices of floating-point elements, and for the FPGA target platform. Prior work is analyzed based on the considered design choices in order to identify the similarities and the differences. The proposed design is implemented using the VHDL hardware description language. The implementation is used to verify the correctness of the design and to confirm the analysis of the design decisions. Correctness is verified both by simulation using the ModelSim i Abstract logic simulator, and in hardware through compiling the implementation using the Altera Quartus II CAD software and testing it on the Altera DE4 board, featuring a Stratix IV EP4SGX530C2 FPGA device. The implementation supports a range of parameters to facilitate the experimental evaluation of design choices. Experimental results show that the design scales linearly with respect to the consumed resources. Although increasing the system size reduces the maximum operating frequency, it also increases the parallelism, resulting in a higher performance. For instance, with 8 floating-point arithmetic units, the system runs at 320 MHz, which corresponds to a performance of 4 GFLOPS, whereas with 64 arithmetic units, it runs at 160 MHz, which corresponds to a performance of 16 GFLOPS. It is also shown that using a transfer schedule based on inner products reduces the transfer time by up to 50% compared to other schedules. Although using square blocks minimizes the number of required block multiplications, other non-square blocks minimize the transfer time, resulting in better total times. I would like to express my gratitude to my supervisor, Dr. Naraig Manjikian, for his continuous guidance and valuable insight, and for his generosity with his time. I am inspired by his dedication to providing effective education and by his attention to detail. I would like to thank my wife, Arwa, and our children, Yazeed, Sahar, and our newest addition, Jana, for their patience and their support, and for the sacrifices they had to make. I am also thankful to my parents for their inspiration and encouragement, and for teaching me to be a lifelong student and seeker of knowledge. I would like to thank King Fahd University of Petroleum & Minerals in Dhahran, Saudi Arabia, for providing the funding for my graduate studies. Hardware and software support for pursuing the implementation effort in this research was provided by CMC Microsystems and Altera Corporation.
A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. I... more A wireless sensor network is made up of sensor nodes connected to data-gathering base stations. In essence, each sensor node is a small form-factor, potentially miniature, battery-powered device, comprising processing, memory, RF transceiver, and sensing modules. Facilitating remote interaction with the physical world, wireless sensor networks are becoming increas-ingly ubiquitous. Demanding diverse service and performance requirements, environmental, agricultural, industrial, consumer, automotive, healthcare, and military applications utilize such networks. In addition, microscopic, and subsequent nanoscopic, wireless sensor networks are envisaged in the future, with positive ramifications for numerous fields and disciplines. In this paper, we comprehensively study the performance of autonomous wireless sensor networks. The paper considers randomized, contention-free, and hybrid medium access technologies. Specif-ically, it investigates the performance of IEEE 802.15.4 slotted CSMA...
ABSTRACT This paper describes performance optimizations of a transfer controller for an FPGA-base... more ABSTRACT This paper describes performance optimizations of a transfer controller for an FPGA-based blocked parallel matrix multiplication accelerator. One of the key challenges of the controller is the generation of a sequence of host memory addresses to transfer blocks of matrices between host and on-chip memories. These addresses are not contiguous, thereby introducing complexity for the controller design. This paper first outlines the intended system architecture for this controller. Next, detailed controller specifications are presented for generating host memory addresses. Various pipeline configurations that yield incremental performance improvements are then described. Finally, experimental results are presented, with the best configuration having an operating frequency exceeding 470 MHz on an Altera Stratix III chip. This level of performance is comparable to that of the pipelined floating-point arithmetic units in the complete system.
Abstract FPGA technology constitutes an attractive platform for high-performance accelerators of ... more Abstract FPGA technology constitutes an attractive platform for high-performance accelerators of parallel workloads in general-purpose computers. Matrix multiplication is a computationally intensive application that is highly parallelizable. Previous work has ...
IEEE 802.15.4 is a low-power, low-rate MAC/PHY standard that meets most of the stringent requirem... more IEEE 802.15.4 is a low-power, low-rate MAC/PHY standard that meets most of the stringent requirements of singlehop wireless sensor networks. Sensor networks with nodal populations composed of thousands of devices have been envisioned in conjunction with environmental, vehicular, military applications, and many others. However, such large sensor network deployments necessitate multihop support as well as low power consumption. In the light of the standard's extremely limited joint support of the two aforementioned attributes, this paper presents two essential contributions. First, a framework is proposed to implement a new IEEE 802.15.4 operating mode, namely, the synchronized peer-to-peer mode. This mode is designed to enable the standard's low-power features in peer-to-peer multihop-ready topologies. The second contribution is a distributed GTS (dGTS) management scheme designed to function in the newly devised network mode. This protocol provides reliable contention-free access in peer-topeer topologies in a completely distributed manner. Assuming optimal routing, our simulation experiments reveal perfect delivery ratios as long as the traffic load does not reach or surpass its saturation threshold. dGTS sustains at least twice the delivery ratio of contention-based access under suboptimal dynamic routing. Moreover, the dGTS scheme exhibits minimum power consumption by eliminating the retransmissions attributed to contention, which, in turn, reduces the number of transmissions to a minimum.
Canadian Journal of Electrical and Computer Engineering, 2014
This paper considers blocking and scheduling for the design and implementation of field-programma... more This paper considers blocking and scheduling for the design and implementation of field-programmable gate array (FPGA)-based floating-point parallel matrix multiplication in the presence of a memory hierarchy. For high performance, on-chip memory holds data that are reused when the computation is divided into blocks, and multiple arithmetic units perform independent operations within each block in parallel. The first contribution of this paper is a detailed analysis of the design space to characterize performance based on the amount of on-chip memory used and the approaches considered for blocking and scheduling of the computation. A comparison is also made to prior work with a unified view. The second contribution is a flexible high-performance implementation for the Altera Stratix IV EP4SGX530C2 FPGA with an interface to external double-data-rate synchronous dynamic RAM DDR2 SDRAM) memory. Various configuration options support optimization of different objectives, and the resulting configurations have been verified in simulation and in hardware. For double-precision floating-point, a performance of 16 giga-floating-point operations per second (GFLOPS) is achievable with 64 arithmetic units at 160 MHz. Résumé-Cet article traite le blocage et la planification pour la conception et l'implémentation d'une multiplication matricielle parallèle à virgule flottante en utilisant un circuit logique programmable (FPGA) avec une hiérarchie de mémoire. Pour atteindre des hautes performances, une mémoire sur puce contient des données qui sont réutilisées lorsque le calcul est divisé en sous blocs, et plusieurs unités arithmétiques réalisent des opérations indépendantes dans chaque bloc en parallèle. La première contribution de cet article est une analyse détaillée de l'espace de conception pour caractériser la performance basée sur la quantité de mémoire sur puce utilisée et les approches envisagées pour le blocage et l'ordonnancement du calcul. Une comparaison normalisée est également présentée par rapport à des travaux antérieurs. La seconde contribution est une implémentation haute performance et flexible sur un FPGA Altera Stratix IV EP4SGX530C2 avec une interface pour une mémoire externe synchrone et dynamique à double débit de données (DDR2 SDRAM). Plusieurs options de configuration pour optimiser différents objectifs, et des configurations subséquentes ont été vérifiées par des simulations ainsi que par implémentation. Pour doubler la précision en virgule flottante, une performance de 16 opérations de giga-virgule flottante par seconde (GFLOPS) est réalisée avec 64 unités arithmétiques à 160 MHz.
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Papers by Ahmad Khayyat