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Rui Rodrigues

International Society of Cyber Security Professionals, Cyber Security, Emeritus

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Krzysztof Krakowski

Cardinal Stefan Wyszynski University in Warsaw

Florida State University

Instituto Nacional de Matematica Pura e Aplicada IMPA

Helmut Pottmann

Tu Wien

UCLouvain (University of Louvain)

paulo V R carvalho

Science Park Research Organization & Counselling

Universidad de Alcala

Delfim F. M. Torres

University of Aveiro

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Papers by Rui Rodrigues

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

This paper presents an infrastructure to test the functionality of the specific architectures out... more This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

PIPELINING SEQUENCES OF LOOPS: A FIRST EXAMPLE

Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme ... more Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme to pipeline those sequences of loops in such a way that subsequent loops can start execution before the end of the previous ones. It uses a hardware scheme with decoupled and concurrent datapath and control units that start execution at the same time. The communication of data items between two loops in sequence is conducted by memories. Each element of one of such memories is responsible to flag the availability of the data requested by a subsequence loop. Thus, the control execution of subsequent loops is also orchestrated by data availability and out-of-order produced-consumed pairs are permitted. We apply the concept to a real example: a fast DCT algorithm.

A TEST INFRASTRUCTURE FOR COMPILERS TARGETING FPGAS

$Figure 3. Speed, Area and Space-Time plots for the various FIR hardware designs As the results reveal the design resulting from the application of scalar replacement can be almost twice as fast and up to 4 times larger. More importantly however, is the fact that exploiting scalar replacement does not always lead to an improved performance. Not only is the design resulting from version v2 slower (mainly due to the degradation of the clock period) but it is also larger than the reference design. Furthermore, the design resulting from code version v4 can be as fast as the design from code version v3 at a fraction of the area. clock cycle when compared to register accesses. In terms of the attained clock period we observe a strong degradation for v2 and v3, compared to v/. This is consistent with the increase in the number of slices the each design requires, as typically larger designs will exhibit longer clock period. Code version v4, however, exhibits an excellent clock period which we attribute to the compactness of the design — the smallest of all. Notice that even though version v4 incurs the time penalty of memory accesses, because of its lower clock period, it exhibits a wall clock performance superior to code version v3 which exclusively uses registers. We plot in figure 3 the wall-clock time and area of the hardware design corresponding to each code version. In the two left plots, the lower the bar the faster and smaller the design. In the rightmost plot we depict in a space-time plot the location of each design where both axes are normalized with respect to the design resulting from code version v/. In this plot the closest a design is plotted to the origin the better as it is a: a a! (a? a: ne: ee i: ee ; a: ee 1$

$Table 2: ID capacity and throughput at 125 MHz (V2P7) Due to the limited capacity of the V2P7, only a frac our reference board. As a means of investigating larger rule sets, we adapted the design to target the Xilinx V2P100 FPGA. We generated 16-, 32-, and 64-bit (1,299 rules with 17,514 characters), and compiled While the 64-bit design was too large to syn hesize, the 16- and 32-bit designs compiled in approximate ion of the default Snort rule set could be implemented in ID cores that implemented the complete Snort rule set NIDS designs that implemented a single filter bridge. y 36 hours. The 16-bit design utilized 32% of the chip’s LUTs and 47% of its slices, while the 32-bit design utilized 36% of the LUTs and 74% of the s ices. T he maximum clock rate for these designs dropped 0 75 MHz. Although the large designs could not achieve a 2x clock rate, the 32-bit design using a 1x clock rate is capable of supporting the complete Snort ru routed design revealed that the compilation designs. e set for one filter bridge. A close inspection of the placed and ools had placed the NI modules and ID unit at opposite ends of the chip. While the V2P100 clearly has the capacity for implementing the complete Snort rule set, this test indicates that additional placement guidance is necessary to meet desired timing requirements in arge$

$Tabela 1: Resouces usage: RAM Memory (Mem), Logical Elements (LE), and fraction of Logical Elemen used (LE(%)); Base: EP1S10F780C6 FPGA The number of samples used during the training phase of the neural network plays a significant role in the efficiency of the recognition process. In order to determine that 50 samples of each gesture were enough, the values of the neural network counter for each recognition operation were analyzed. The adopted neural network model allows the counter to vary between 0 to 95, the greatest value determining the winner pattern of the recognition process. By analyzing the difference between counters, it was concluded that using less than 50 samples in the training process results in small differences between the winner pattern and the others. This clearly indicates a low confidence degree. On the other hand, using more than 50 samples for training tends to saturate the neural network, as a large number of counters become close to the maximum value. This also reduces the confidence degree.$

On Pipelining Sequences of Data-Dependent Loops

Journal of Universal Computer Science, 2007

Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many a... more Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually perform computations (with loop intensive behavior) and produce new data to be consumed by subsequent tasks. This paper shows a scheme to pipeline sequences of data-dependent loops, in such a way that subsequent loops can start execution before the completion of the previous ones, which achieves performance improvements. It uses a ...

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops

Many video and image/signal processing applications can be structured as sequences of data-depend... more Many video and image/signal processing applications can be structured as sequences of data-dependent tasks using a consumer/producer communication paradigm and are therefore amenable to pipelined execution. This paper presents an execution technique to speed-up the overall execution of successive, data-dependent tasks on a reconfigurable architecture. The technique pipelines sequences of data-dependent tasks by overlapping their execution subject to data-dependences. It decouples the concurrent data-path and control units and uses a custom, application data-driven, fine-grained synchronization and buffering scheme. In addition, the execution scheme allows for out-of- order, but data-dependent producer-consumer pairs not allowed by previous data-driven pipelining approaches. The approach has been exploited in the context of a high-level compiler targeting FPGAs. The preliminary experimental results reveal noticeable performance improvements and buffer size reductions for a number of benchmarks over traditional approaches.

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

A two-step algorithm of smooth spline generation on Riemannian manifolds

Journal of Computational and Applied Mathematics, 2006

This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoot... more This paper presents a simple geometric algorithm to generate splines of arbitrary degree of smoothness in Euclidean spaces. Unlike other existing methods, this simple geometric algorithm does not require a recursive procedure and, consequently, introduces a significant reduction in calculation time. The algorithm is then extended to other complete Riemannian manifolds, namely to matrix Lie groups and spheres.

Smooth trajectory planning for fully automated passengers vehicles - spline and clothoid based methods and its simulation

A new approach for mobility, providing an alternative to the private passenger car, by offering t... more A new approach for mobility, providing an alternative to the private passenger car, by offering the same flexibility but with much less nuisances, is emerging, based on fully automated electric vehicles. A fleet of such vehicles might be an important element in a novel individual, door-to-door, transportation system to the city of tomorrow. For fully automated operation, trajectory planning methods that produce smooth trajectories, with low associated accelerations and jerk, for providing passenger´s comfort, are required. This paper addresses this problem proposing an approach that consists of introducing a velocity planning stage to generate adequate time sequences for usage in the interpolating curve planners. Moreover, the generated speed profile can be merged into the trajectory for usage in trajectory-tracking tasks like it is described in this paper, or it can be used separately (from the generated 2D curve) for usage in pathfollowing tasks. Three trajectory planning methods, aided by the speed profile planning, are analysed from the point of view of passengers' comfort, implementation easiness, and trajectory tracking.

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

This paper presents an infrastructure to test the functionality of the specific architectures out... more This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

PIPELINING SEQUENCES OF LOOPS: A FIRST EXAMPLE

Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme ... more Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme to pipeline those sequences of loops in such a way that subsequent loops can start execution before the end of the previous ones. It uses a hardware scheme with decoupled and concurrent datapath and control units that start execution at the same time. The communication of data items between two loops in sequence is conducted by memories. Each element of one of such memories is responsible to flag the availability of the data requested by a subsequence loop. Thus, the control execution of subsequent loops is also orchestrated by data availability and out-of-order produced-consumed pairs are permitted. We apply the concept to a real example: a fast DCT algorithm.

A TEST INFRASTRUCTURE FOR COMPILERS TARGETING FPGAS

$Figure 3. Speed, Area and Space-Time plots for the various FIR hardware designs As the results reveal the design resulting from the application of scalar replacement can be almost twice as fast and up to 4 times larger. More importantly however, is the fact that exploiting scalar replacement does not always lead to an improved performance. Not only is the design resulting from version v2 slower (mainly due to the degradation of the clock period) but it is also larger than the reference design. Furthermore, the design resulting from code version v4 can be as fast as the design from code version v3 at a fraction of the area. clock cycle when compared to register accesses. In terms of the attained clock period we observe a strong degradation for v2 and v3, compared to v/. This is consistent with the increase in the number of slices the each design requires, as typically larger designs will exhibit longer clock period. Code version v4, however, exhibits an excellent clock period which we attribute to the compactness of the design — the smallest of all. Notice that even though version v4 incurs the time penalty of memory accesses, because of its lower clock period, it exhibits a wall clock performance superior to code version v3 which exclusively uses registers. We plot in figure 3 the wall-clock time and area of the hardware design corresponding to each code version. In the two left plots, the lower the bar the faster and smaller the design. In the rightmost plot we depict in a space-time plot the location of each design where both axes are normalized with respect to the design resulting from code version v/. In this plot the closest a design is plotted to the origin the better as it is a: a a! (a? a: ne: ee i: ee ; a: ee 1$

$Table 2: ID capacity and throughput at 125 MHz (V2P7) Due to the limited capacity of the V2P7, only a frac our reference board. As a means of investigating larger rule sets, we adapted the design to target the Xilinx V2P100 FPGA. We generated 16-, 32-, and 64-bit (1,299 rules with 17,514 characters), and compiled While the 64-bit design was too large to syn hesize, the 16- and 32-bit designs compiled in approximate ion of the default Snort rule set could be implemented in ID cores that implemented the complete Snort rule set NIDS designs that implemented a single filter bridge. y 36 hours. The 16-bit design utilized 32% of the chip’s LUTs and 47% of its slices, while the 32-bit design utilized 36% of the LUTs and 74% of the s ices. T he maximum clock rate for these designs dropped 0 75 MHz. Although the large designs could not achieve a 2x clock rate, the 32-bit design using a 1x clock rate is capable of supporting the complete Snort ru routed design revealed that the compilation designs. e set for one filter bridge. A close inspection of the placed and ools had placed the NI modules and ID unit at opposite ends of the chip. While the V2P100 clearly has the capacity for implementing the complete Snort rule set, this test indicates that additional placement guidance is necessary to meet desired timing requirements in arge$

$Tabela 1: Resouces usage: RAM Memory (Mem), Logical Elements (LE), and fraction of Logical Elemen used (LE(%)); Base: EP1S10F780C6 FPGA The number of samples used during the training phase of the neural network plays a significant role in the efficiency of the recognition process. In order to determine that 50 samples of each gesture were enough, the values of the neural network counter for each recognition operation were analyzed. The adopted neural network model allows the counter to vary between 0 to 95, the greatest value determining the winner pattern of the recognition process. By analyzing the difference between counters, it was concluded that using less than 50 samples in the training process results in small differences between the winner pattern and the others. This clearly indicates a low confidence degree. On the other hand, using more than 50 samples for training tends to saturate the neural network, as a large number of counters become close to the maximum value. This also reduces the confidence degree.$

On Pipelining Sequences of Data-Dependent Loops

Journal of Universal Computer Science, 2007

Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many a... more Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually perform computations (with loop intensive behavior) and produce new data to be consumed by subsequent tasks. This paper shows a scheme to pipeline sequences of data-dependent loops, in such a way that subsequent loops can start execution before the completion of the previous ones, which achieves performance improvements. It uses a ...

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops

Many video and image/signal processing applications can be structured as sequences of data-depend... more Many video and image/signal processing applications can be structured as sequences of data-dependent tasks using a consumer/producer communication paradigm and are therefore amenable to pipelined execution. This paper presents an execution technique to speed-up the overall execution of successive, data-dependent tasks on a reconfigurable architecture. The technique pipelines sequences of data-dependent tasks by overlapping their execution subject to data-dependences. It decouples the concurrent data-path and control units and uses a custom, application data-driven, fine-grained synchronization and buffering scheme. In addition, the execution scheme allows for out-of- order, but data-dependent producer-consumer pairs not allowed by previous data-driven pipelining approaches. The approach has been exploited in the context of a high-level compiler targeting FPGAs. The preliminary experimental results reveal noticeable performance improvements and buffer size reductions for a number of benchmarks over traditional approaches.