Efficient architectural solutions for systems based on shared memory processor clusters are prese... more Efficient architectural solutions for systems based on shared memory processor clusters are presented in the paper. In the proposed architecture, processors can be dynamically switched between bus-based SMP clusters at program run-time. A switched processor can bring data in its cache that can be read on the fly by processors in the cluster when written into the cluster memory. This new inter-cluster data transfer paradigm is called communication on the fly. For execution in the proposed architecture, programs are structured accordingly to macro-data flow graphs in which task composition and communication are so defined, as to eliminate reloading of data caches during task execution. An extended macro-data flow graph representation is presented in the paper. It enables modeling of program execution control in the system including parallel task execution, data cache functioning, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly. Simulation results for a very fine-grained parallel numerical example are presented.
Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of secu... more Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of security scenarios, namely how the number of agents and their task assignment impact the performance, e.g. attack time, of strategies executed by opposing coalitions. Optimal scheduling of agents' actions, a non-trivial problem, is thus vital. We discuss associated caveats and propose an algorithm that synthesises such an assignment, targeting minimal attack time and using the minimal number of agents for a given attack-defence tree. We also investigate an alternative approach for the same problem using Rewriting Logic, starting with a simple and elegant declarative model, whose correctness (in terms of schedule's optimality) is self-evident. We then refine this specification, inspired by the design of our specialised algorithm, to obtain an efficient system that can be used as a playground to explore various aspects of attack-defence trees. We compare the two approaches on different benchmarks.
The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters wit... more The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters with communication on the fly for massively parallel fine grain numerical computations. It is assumed that the proposed architecture is implemented using the highly modular "system on chip" and "network on chip" technology. This technology is considered to provide soon a very large number of co-operating processors embedded in a single parallel system, thus enabling massively parallel computations. The proposed architecture of dynamic clusters with communication on the fly meets requirements of large scale fine grain computations and can be successfully applied in this technology. Experimental simulation results are presented concerning efficiency of fine grain parallel implementation of a typical numerical problem which is matrix multiplication based on recursive data decomposition. Selection of optimal parallel computation grain is discussed. Estimations of the efficiency of the proposed methods for fine grain computations for large problem size are presented
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
This paper presents a possible extension of the Open MP library for programming parallel multithr... more This paper presents a possible extension of the Open MP library for programming parallel multithreaded computations in the architecture of dynamic SMP clusters with communication on the fly. Dynamic SMP clusters are composed of processors directly connected to the same local shared memory modules with the composition of the clusters arranged at program runtime. Inter-processor communication in such clusters is
Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
The paper concerns task graph scheduling in parallel programs for a parallel architecture based o... more The paper concerns task graph scheduling in parallel programs for a parallel architecture based on dynamic SMP processor clusters with data transmissions on the fly. The assumed executive computer architecture consists of a set of NoC modules, each containing a set of processors and memory blocks connected via a local interconnection network. NoC modules are connected via a global interconnection network. An algorithm for scheduling parallel program graphs is presented, which decomposes an initial program graph into sub-graphs, which are then mapped to NoC modules, reducing global communication between modules. Then these subgraphs are structured inside the modules to include reads on the fly and processor switching. Reads on the fly reduce execution time of the program by elimination of read operations in linear program execution time.
This paper deals with iterative algorithm of reconstruction of 2D tomographic scans. The relative... more This paper deals with iterative algorithm of reconstruction of 2D tomographic scans. The relative speedup of the reconstruction process as well as real–time and high fidelity imaging can be improved by implementation of distributed processing. The properties of the sequential algorithm are studied, and the scheme of coloring of projections is introduced in the concurrent version of the presented algorithm. The details of the elaborated distributed implementation of the ART (Algebraic Reconstruction Technique) are presented. Parallel implementation in a system based on dynamically configurable SMP clusters is proposed followed by performance analysis.
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering, 2011
Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks consti... more Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks constitute now a feasible solution, which brings back to life challenges of massively parallel systems. The paper presents new methods for data communication inside CMP modules and for inter-CMP-module data communication. Inside CMP modules data communication through shared variables is improved by the use of dynamic core switching between core clusters organized in a system of multi-level caches with data reads on the fly. At the level of global data communication between CMP modules a special network implements communication between CMP module external shared memories with simultaneous reads on the fly to L2 data caches and main memories of CMP modules. Programs are built following a macro data flow graph paradigm.
The paper presents a comparative analysis of parallel implementation of the preconditioned conjug... more The paper presents a comparative analysis of parallel implementation of the preconditioned conjugate gradient method with symmetric successive over relaxation preconditioner. Two parallel implementations are compared. The first one is a message passing version that turned out to be inefficient when executed on a typical cluster of workstations. The other one is an efficient version simulated on a novel architecture of dynamically reconfigurable shared memory clusters with a new paradigm of inter-processor communication called communication on the fly. The presented example shows high suitability of the proposed architecture for fine grain numerical computations what can be very useful in simulation of physical phenomena described as numerical problems for fine grain parallel execution.
The paper presents a comparative analysis of parallel implementation of the preconditioned conjug... more The paper presents a comparative analysis of parallel implementation of the preconditioned conjugate gradient method with the symmetric-successive over-relaxation preconditioner. Two parallel implementations of the matrix solver are compared. The first one is a message-passing version executed on a cluster of workstations. The other one is an efficient version simulated on a novel architecture of dynamically reconfigurable shared memory clusters with a new paradigm of inter-processor communication called communication on the fly. The presented example shows high suitability of the proposed architecture for fine grain numerical computations. It can be very useful in the simulation of physical phenomena described as numerical problems suitable for fine grain parallel execution.
The 4th International Symposium on Parallel and Distributed Computing (ISPDC'05)
The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on... more The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on multiple dynamic SMP clusters. Processors can be switched between shared memory modules in the runtime. Memory modules and processors are organized in computational system on chip modules of a fixed size and are inter-connected by a local communication network implemented in a network-on-chip technology (NoC). Processors located in the same SoC module can share their data and communicate using a technique of data transfers on the fly. A number of such SoC modules can be connected using a global interconnection network to form a larger infrastructure. The presented algorithm schedules initial macro dataflow program graph for such an architecture with a given number of SoC modules, considering a fixed size of a module. First, it distributes program graph nodes among processors, assuming no distribution between SoC modules. Then it transforms and schedules computations and communications to use processor switching and read on the fly facilities. Finally, using genetic algorithm, it divides the whole set of processors into subsets of a given size, which then are mapped to separate SoC modules
Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of secu... more Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of security scenarios, namely how the number of agents and their task assignment impact the performance, e.g. attack time, of strategies executed by opposing coalitions. Optimal scheduling of agents’ actions, a non-trivial problem, is thus vital. We discuss associated caveats and propose an algorithm that synthesises such an assignment, targeting minimal attack time and using minimal number of agents for a given attack-defence tree. The complexity of the algorithm is proved to be quadratic in the number of the attack-defence tree nodes.
The paper presents results of experimental work in the field of optimization of parallel, event-d... more The paper presents results of experimental work in the field of optimization of parallel, event-driven simulation via application of global state monitoring. Discrete event simulation is a well known technique used for modelling and simulating complex parallel systems. Parallel simulation employs multiple simulated event queues processed in parallel. Absence of proper synchronization between parallel queues can cause massive simulation rollbacks, which slow down the simulation process. We propose a new method for parallel simulation control with monitoring of global program states, which prevent excessive number of rollbacks. Every queue process reports its local progress to a global synchronizer which monitors the global simulation state as timestamps of recently processed events in distributed queues. Based on this state the synchronizer checks the progress of simulation and sends signals limiting progress in too advanced queues. This control is done asynchronously, and thus it ha...
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
The exponential computational cost involved in traditional data mining methods enforces search fo... more The exponential computational cost involved in traditional data mining methods enforces search for less complex new algorithms. Especially, data mining on grid is a challenge due to the lack of shared memory in grid computing, which puts special attention to communication optimization. The aim of the DisDaMin project (distributed data mining), described in the paper, is solving data mining problems
2009 Eighth International Symposium on Parallel and Distributed Computing, 2009
The paper presents a method for the optimized control of program execution in modular systems bas... more The paper presents a method for the optimized control of program execution in modular systems based on chip multiprocessor (CMP) modules interconnected by a special global interconnection network. The applied CMP modules are based on communication on the fly, which is a novel efficient group communication paradigm implemented inside the interconnection network. Communication on the fly is based on a synergy of dynamic processor switching between memory modules and data read on the fly mechanism, which enables to many processors simultaneous reads of data, when present on shared memory buses. The paper presents a two-stage scheduling algorithm for programs expressed in a graph notation. The first stage schedules program tasks inside the CMP modules using an algorithm based on the notion of moldable tasks. In the result, a scheduled program moldable task graph is produced. The moldable task graph is next structurized for optimized communication execution in the global network working according to the look-ahead link connection setting paradigm. Results of simulation experiments evaluate the efficiency and other properties of the proposed architectural solution.
2011 10th International Symposium on Parallel and Distributed Computing, 2011
A new distributed program graphical design environment is described in the paper. It is oriented ... more A new distributed program graphical design environment is described in the paper. It is oriented towards designing program execution control based on a built-in system infrastructure which enables easy global application states monitoring in systems based on multicore processors. Two aspects of global application control design are covered. First is the global control flow in programs at the level of
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering, 2011
A new framework for designing evolved program execution control in distributed programs is discus... more A new framework for designing evolved program execution control in distributed programs is discussed in the paper. The framework provides an infrastructure for designing distributed program control based on monitoring of global application states. Global control constructs are proposed which logically bind distributed program modules and define the flow of control dependent on the monitoring of global application states. Such
System on chip (SoC) computing [1] and emerging ultra high scale integration technology are curre... more System on chip (SoC) computing [1] and emerging ultra high scale integration technology are currently susceptible to provide SoC modules embedding dozens of processors, inter–processor communication network and shared memory modules in a single chip. At the same time, the interconnection–centric SoC design [2] is seeking for new efficient inter-processor communication mechanisms, which condition reasonable use of so many processors on a chip. The success at the architectural and technological levels can not be consumed without adequate tools for automatic program design, particulary for parallel program task scheduling.
Efficient architectural solutions for systems based on shared memory processor clusters are prese... more Efficient architectural solutions for systems based on shared memory processor clusters are presented in the paper. In the proposed architecture, processors can be dynamically switched between bus-based SMP clusters at program run-time. A switched processor can bring data in its cache that can be read on the fly by processors in the cluster when written into the cluster memory. This new inter-cluster data transfer paradigm is called communication on the fly. For execution in the proposed architecture, programs are structured accordingly to macro-data flow graphs in which task composition and communication are so defined, as to eliminate reloading of data caches during task execution. An extended macro-data flow graph representation is presented in the paper. It enables modeling of program execution control in the system including parallel task execution, data cache functioning, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly. Simulation results for a very fine-grained parallel numerical example are presented.
Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of secu... more Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of security scenarios, namely how the number of agents and their task assignment impact the performance, e.g. attack time, of strategies executed by opposing coalitions. Optimal scheduling of agents' actions, a non-trivial problem, is thus vital. We discuss associated caveats and propose an algorithm that synthesises such an assignment, targeting minimal attack time and using the minimal number of agents for a given attack-defence tree. We also investigate an alternative approach for the same problem using Rewriting Logic, starting with a simple and elegant declarative model, whose correctness (in terms of schedule's optimality) is self-evident. We then refine this specification, inspired by the design of our specialised algorithm, to obtain an efficient system that can be used as a playground to explore various aspects of attack-defence trees. We compare the two approaches on different benchmarks.
The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters wit... more The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters with communication on the fly for massively parallel fine grain numerical computations. It is assumed that the proposed architecture is implemented using the highly modular "system on chip" and "network on chip" technology. This technology is considered to provide soon a very large number of co-operating processors embedded in a single parallel system, thus enabling massively parallel computations. The proposed architecture of dynamic clusters with communication on the fly meets requirements of large scale fine grain computations and can be successfully applied in this technology. Experimental simulation results are presented concerning efficiency of fine grain parallel implementation of a typical numerical problem which is matrix multiplication based on recursive data decomposition. Selection of optimal parallel computation grain is discussed. Estimations of the efficiency of the proposed methods for fine grain computations for large problem size are presented
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
This paper presents a possible extension of the Open MP library for programming parallel multithr... more This paper presents a possible extension of the Open MP library for programming parallel multithreaded computations in the architecture of dynamic SMP clusters with communication on the fly. Dynamic SMP clusters are composed of processors directly connected to the same local shared memory modules with the composition of the clusters arranged at program runtime. Inter-processor communication in such clusters is
Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
The paper concerns task graph scheduling in parallel programs for a parallel architecture based o... more The paper concerns task graph scheduling in parallel programs for a parallel architecture based on dynamic SMP processor clusters with data transmissions on the fly. The assumed executive computer architecture consists of a set of NoC modules, each containing a set of processors and memory blocks connected via a local interconnection network. NoC modules are connected via a global interconnection network. An algorithm for scheduling parallel program graphs is presented, which decomposes an initial program graph into sub-graphs, which are then mapped to NoC modules, reducing global communication between modules. Then these subgraphs are structured inside the modules to include reads on the fly and processor switching. Reads on the fly reduce execution time of the program by elimination of read operations in linear program execution time.
This paper deals with iterative algorithm of reconstruction of 2D tomographic scans. The relative... more This paper deals with iterative algorithm of reconstruction of 2D tomographic scans. The relative speedup of the reconstruction process as well as real–time and high fidelity imaging can be improved by implementation of distributed processing. The properties of the sequential algorithm are studied, and the scheme of coloring of projections is introduced in the concurrent version of the presented algorithm. The details of the elaborated distributed implementation of the ART (Algebraic Reconstruction Technique) are presented. Parallel implementation in a system based on dynamically configurable SMP clusters is proposed followed by performance analysis.
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering, 2011
Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks consti... more Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks constitute now a feasible solution, which brings back to life challenges of massively parallel systems. The paper presents new methods for data communication inside CMP modules and for inter-CMP-module data communication. Inside CMP modules data communication through shared variables is improved by the use of dynamic core switching between core clusters organized in a system of multi-level caches with data reads on the fly. At the level of global data communication between CMP modules a special network implements communication between CMP module external shared memories with simultaneous reads on the fly to L2 data caches and main memories of CMP modules. Programs are built following a macro data flow graph paradigm.
The paper presents a comparative analysis of parallel implementation of the preconditioned conjug... more The paper presents a comparative analysis of parallel implementation of the preconditioned conjugate gradient method with symmetric successive over relaxation preconditioner. Two parallel implementations are compared. The first one is a message passing version that turned out to be inefficient when executed on a typical cluster of workstations. The other one is an efficient version simulated on a novel architecture of dynamically reconfigurable shared memory clusters with a new paradigm of inter-processor communication called communication on the fly. The presented example shows high suitability of the proposed architecture for fine grain numerical computations what can be very useful in simulation of physical phenomena described as numerical problems for fine grain parallel execution.
The paper presents a comparative analysis of parallel implementation of the preconditioned conjug... more The paper presents a comparative analysis of parallel implementation of the preconditioned conjugate gradient method with the symmetric-successive over-relaxation preconditioner. Two parallel implementations of the matrix solver are compared. The first one is a message-passing version executed on a cluster of workstations. The other one is an efficient version simulated on a novel architecture of dynamically reconfigurable shared memory clusters with a new paradigm of inter-processor communication called communication on the fly. The presented example shows high suitability of the proposed architecture for fine grain numerical computations. It can be very useful in the simulation of physical phenomena described as numerical problems suitable for fine grain parallel execution.
The 4th International Symposium on Parallel and Distributed Computing (ISPDC'05)
The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on... more The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on multiple dynamic SMP clusters. Processors can be switched between shared memory modules in the runtime. Memory modules and processors are organized in computational system on chip modules of a fixed size and are inter-connected by a local communication network implemented in a network-on-chip technology (NoC). Processors located in the same SoC module can share their data and communicate using a technique of data transfers on the fly. A number of such SoC modules can be connected using a global interconnection network to form a larger infrastructure. The presented algorithm schedules initial macro dataflow program graph for such an architecture with a given number of SoC modules, considering a fixed size of a module. First, it distributes program graph nodes among processors, assuming no distribution between SoC modules. Then it transforms and schedules computations and communications to use processor switching and read on the fly facilities. Finally, using genetic algorithm, it divides the whole set of processors into subsets of a given size, which then are mapped to separate SoC modules
Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of secu... more Expressing attack-defence trees in a multi-agent setting allows for studying a new aspect of security scenarios, namely how the number of agents and their task assignment impact the performance, e.g. attack time, of strategies executed by opposing coalitions. Optimal scheduling of agents’ actions, a non-trivial problem, is thus vital. We discuss associated caveats and propose an algorithm that synthesises such an assignment, targeting minimal attack time and using minimal number of agents for a given attack-defence tree. The complexity of the algorithm is proved to be quadratic in the number of the attack-defence tree nodes.
The paper presents results of experimental work in the field of optimization of parallel, event-d... more The paper presents results of experimental work in the field of optimization of parallel, event-driven simulation via application of global state monitoring. Discrete event simulation is a well known technique used for modelling and simulating complex parallel systems. Parallel simulation employs multiple simulated event queues processed in parallel. Absence of proper synchronization between parallel queues can cause massive simulation rollbacks, which slow down the simulation process. We propose a new method for parallel simulation control with monitoring of global program states, which prevent excessive number of rollbacks. Every queue process reports its local progress to a global synchronizer which monitors the global simulation state as timestamps of recently processed events in distributed queues. Based on this state the synchronizer checks the progress of simulation and sends signals limiting progress in too advanced queues. This control is done asynchronously, and thus it ha...
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
The exponential computational cost involved in traditional data mining methods enforces search fo... more The exponential computational cost involved in traditional data mining methods enforces search for less complex new algorithms. Especially, data mining on grid is a challenge due to the lack of shared memory in grid computing, which puts special attention to communication optimization. The aim of the DisDaMin project (distributed data mining), described in the paper, is solving data mining problems
2009 Eighth International Symposium on Parallel and Distributed Computing, 2009
The paper presents a method for the optimized control of program execution in modular systems bas... more The paper presents a method for the optimized control of program execution in modular systems based on chip multiprocessor (CMP) modules interconnected by a special global interconnection network. The applied CMP modules are based on communication on the fly, which is a novel efficient group communication paradigm implemented inside the interconnection network. Communication on the fly is based on a synergy of dynamic processor switching between memory modules and data read on the fly mechanism, which enables to many processors simultaneous reads of data, when present on shared memory buses. The paper presents a two-stage scheduling algorithm for programs expressed in a graph notation. The first stage schedules program tasks inside the CMP modules using an algorithm based on the notion of moldable tasks. In the result, a scheduled program moldable task graph is produced. The moldable task graph is next structurized for optimized communication execution in the global network working according to the look-ahead link connection setting paradigm. Results of simulation experiments evaluate the efficiency and other properties of the proposed architectural solution.
2011 10th International Symposium on Parallel and Distributed Computing, 2011
A new distributed program graphical design environment is described in the paper. It is oriented ... more A new distributed program graphical design environment is described in the paper. It is oriented towards designing program execution control based on a built-in system infrastructure which enables easy global application states monitoring in systems based on multicore processors. Two aspects of global application control design are covered. First is the global control flow in programs at the level of
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering, 2011
A new framework for designing evolved program execution control in distributed programs is discus... more A new framework for designing evolved program execution control in distributed programs is discussed in the paper. The framework provides an infrastructure for designing distributed program control based on monitoring of global application states. Global control constructs are proposed which logically bind distributed program modules and define the flow of control dependent on the monitoring of global application states. Such
System on chip (SoC) computing [1] and emerging ultra high scale integration technology are curre... more System on chip (SoC) computing [1] and emerging ultra high scale integration technology are currently susceptible to provide SoC modules embedding dozens of processors, inter–processor communication network and shared memory modules in a single chip. At the same time, the interconnection–centric SoC design [2] is seeking for new efficient inter-processor communication mechanisms, which condition reasonable use of so many processors on a chip. The success at the architectural and technological levels can not be consumed without adequate tools for automatic program design, particulary for parallel program task scheduling.
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Papers by Łukasz Maśko