trung diep

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Steffen Boehm

University of Exeter

Armando Marques-Guedes

UNL - New University of Lisbon

Marianna Sigala

University of South Australia

J.-C. Spender

Kozminski University

Professor.Krishan Bir Singh

University of Rajasthan

Juraj Marušiak

Slovak Academy of Sciences

Gordin valery

National Research University Higher School of Economics

Ibrahim B Syed

University of Louisville, KY

Nazir Hussain

Quaid-i-Azam University, Islamabad, Pakistan

Sẽ Ổn Mọi Chuyện

Hanoi National Economics Univesity

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Papers by trung diep

Server Technologies

On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysi... more On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysis of server processors. Typical cached configurations used by researchers to simulate OLTP workloads are orders of magnitude smaller than the fully scaled configurations used by OEM vendors to achieve world-record transaction processing throughput. The objective of this study is to discover the underlying relationships that characterize OLTP performance over a wide range of configurations. To this end, we have derived the “iron law ” of database performance. Using our iron law, we show that both the average instructions executed per transaction (IPX) and the average cycles per instruction (CPI) are critical to the transaction-throughput performance. We use an extensive, empirical examination of an Oracle based commercial OLTP workload on an Intel Xeon multiprocessor system to characterize the scaling behavior of both the IPX and the CPI. We demonstrate that across a wide range of configu...

Systematic validation of pipeline interlock for superscalar microarchitectures

IEEE International Symposium on Fault-Tolerant Computing, Jun 27, 1995

Page 1. Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures Trung A. D... more

Method and apparatus for variable pop hardware return address stack

Performance evaluation of the PowerPC 620 microarchitecture

Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95, 1995

The PowerPC 620TM microprocessor' is the most recent and performance leading member of the PowerP... more The PowerPC 620TM microprocessor' is the most recent and performance leading member of the PowerPCT~i family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch prediction scheme, dynamic renaming for all the register jiles, distributed multi-entry reservation stations, true out-oforder execution by six execution units, and a completion buffer for ensuring precise exceptions. This paper presents an instruction-level performance evaluation of the 620 microarchitectu re. A pe~ormance simulator is developed using the VM W (Visualization-based Microarchitecture Workbench) retargetable framework. The VMW-based simulator accurately models the microarchitecture down to the machine cycle level. Extensive trace-driven simulation is pe~ormed using the SPEC92 benchmarks. Detailed quantitative analyses of the effectiveness of all key microarchitecture features are presented.

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Architecture-compatible code boosting for performance enhancement of the IBM RS/6000

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

ABSTRACT

Branch behavior of a commercial OLTP workload on Intel IA32 processors

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

Abstract This paper presents a detailed branch characterization of an Oracle based commercial on-... more

Scaling and characterizing database workloads: bridging the gap between research and practice

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysi... more On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysis of server processors. Typical cached configurations used by researchers to simulate OLTP workloads are orders of magnitude smaller than the fully scaled configurations used by OEM vendors to achieve world-record transaction processing throughput. The objective of this study is to discover the underlying relationships that characterize OLTP performance over a wide range of configurations. To this end, we have derived the "iron law" of database performance. Using our iron law, we show that both the average instructions executed per transaction (IPX) and the average cycles per instruction (CPI) are critical to the transaction-throughput performance. We use an extensive, empirical examination of an Oracle based commercial OLTP workload on an Intel Xeon multiprocessor system to characterize the scaling behavior of both the IPX and the CPI. We demonstrate that across a wide range of configurations the IPX and CPI behavior follows predictable trends, which can be accurately characterized by simple linear or piece-wise linear approximations. Based on our data, we propose a method for selecting a minimal, representative workload configuration from which behaviors of much larger OLTP configurations can be accurately extrapolated.

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A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News, 2004

Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on c... more Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors. This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP). Our results show that, although, the overall code footprint of ODB is large, multiple ODB threads running concurrently on multiple processors tend to access common code segments frequently, thus exhibiting significant constructive sharing. In fact, in a CMP system, an I-cache shared between multiple processors incurs similar miss rate as a dedicated I-cache per processor where the per processor I-cache has the same capacity as the shared I-cache. Based on these observations, this paper makes the case for a shared I-cache organization in a CMP, instead of the traditional approach of using a dedicated I-cache per processor.Furthermore, this paper shows that OLTP code stream exhibits good spatial locality. Adding a simple dedi...

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Performance Advantage of the Register Stack in Intel® Itanium™ Processors

The Intel® Itanium™ architecture provides a virtual register stack of unlimited size for use by s... more The Intel® Itanium™ architecture provides a virtual register stack of unlimited size for use by software. New virtual registers are allocated on a procedure call and deallocated on return. Itanium processors implement the register stack by means of a large physical register file, a mapping from virtual to physical registers, and a Register Stack Engine (RSE) that saves and restores the contents of the physical registers to memory without explicit program intervention. The combination of these features significantly reduces the number of loads and stores required to save registers across procedure calls compared to a conventional architecture. In this paper, we show that the Itanium register stack reduces load and store traffic to the stack by a t least a factor of three across select SpecInt2000 and Oracle database benchmarks. Furthermore, we examine the effects of the register stack on data cache miss rates and program execution time. When compared to a conventional architecture, t...

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VMW: a visualization-based microarchitecture workbench

Computer, 1995

Superscalar processor design requires increasingly sophisticated software tools. The visualizatio... more

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Scheduling optimizations for user-level threads

Server Technologies

Systematic validation of pipeline interlock for superscalar microarchitectures

IEEE International Symposium on Fault-Tolerant Computing, Jun 27, 1995

Page 1. Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures Trung A. D... more

Method and apparatus for variable pop hardware return address stack

Performance evaluation of the PowerPC 620 microarchitecture

Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95, 1995

Download

Architecture-compatible code boosting for performance enhancement of the IBM RS/6000

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

ABSTRACT

Branch behavior of a commercial OLTP workload on Intel IA32 processors

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

Abstract This paper presents a detailed branch characterization of an Oracle based commercial on-... more

Scaling and characterizing database workloads: bridging the gap between research and practice

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysi... more On-Line Transaction Processing (OLTP) workloads are crucial benchmarks for the design and analysis of server processors. Typical cached configurations used by researchers to simulate OLTP workloads are orders of magnitude smaller than the fully scaled configurations used by OEM vendors to achieve world-record transaction processing throughput. The objective of this study is to discover the underlying relationships that characterize OLTP performance over a wide range of configurations. To this end, we have derived the "iron law" of database performance. Using our iron law, we show that both the average instructions executed per transaction (IPX) and the average cycles per instruction (CPI) are critical to the transaction-throughput performance. We use an extensive, empirical examination of an Oracle based commercial OLTP workload on an Intel Xeon multiprocessor system to characterize the scaling behavior of both the IPX and the CPI. We demonstrate that across a wide range of configurations the IPX and CPI behavior follows predictable trends, which can be accurately characterized by simple linear or piece-wise linear approximations. Based on our data, we propose a method for selecting a minimal, representative workload configuration from which behaviors of much larger OLTP configurations can be accurately extrapolated.

Download

A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News, 2004

Download

Performance Advantage of the Register Stack in Intel® Itanium™ Processors

Download

VMW: a visualization-based microarchitecture workbench

Computer, 1995

Superscalar processor design requires increasingly sophisticated software tools. The visualizatio... more

Download

Scheduling optimizations for user-level threads

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