Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification d... more The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification depend on the availability of a high performance package to manipulate very large BDDs. State-ofthe-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using an iterative breadth-first technique directed towards localizing the memory accesses to exploit the memory system hierarchy. The new memory-oriented performance features of this package are 1) an architecture independent customized memory management scheme, 2) the ability to issue multiple independent BDD operations (superscalarity), and 3) the ability to perform multiple BDD operations even when the operands of some BDD operations are the result of some other operations yet to be completed (pipelining). A comprehensive set of BDD manipulation algorithms are implemented using the above techniques. Unlike the breadth-first algorithms presented in the literature, the new package is faster than the state-of-the-art BDD package by a factor of upto 1.5, even for the BDD sizes that fit within the main memory. For BDD sizes that do not fit within the main memory, a performance improvement of more than a factor of 1000 can be achieved.
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
Page 1. Using Combinational Verification for Sequential Circuits Rajeev K. Ranjan Vigyan Singhal ... more Page 1. Using Combinational Verification for Sequential Circuits Rajeev K. Ranjan Vigyan Singhal Fabio Somenzi Robert K. Brayton [email protected][email protected][email protected][email protected] Synopsys Inc. ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
International Conference on Computer Aided Design, 1998
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of... more Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a decade, its exact optimization capability has not been formally established. We show that retiming and resynthesis can exactly implement 1-step equivalent state transition graph transformations. This result is the strongest to date. We also show how the notions of retiming and resynthesis can be moderately extended to achieve more powerful state transition graph transformations. Our work will provide theoretical foundation for practical retiming and resynthesis based optimization and verification.
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification d... more The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification depend on the availability of a high performance package to manipulate very large BDDs. State-ofthe-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using an iterative breadth-first technique directed towards localizing the memory accesses to exploit the memory system hierarchy. The new memory-oriented performance features of this package are 1) an architecture independent customized memory management scheme, 2) the ability to issue multiple independent BDD operations (superscalarity), and 3) the ability to perform multiple BDD operations even when the operands of some BDD operations are the result of some other operations yet to be completed (pipelining). A comprehensive set of BDD manipulation algorithms are implemented using the above techniques. Unlike the breadth-first algorithms presented in the literature, the new package is faster than the state-of-the-art BDD package by a factor of upto 1.5, even for the BDD sizes that fit within the main memory. For BDD sizes that do not fit within the main memory, a performance improvement of more than a factor of 1000 can be achieved.
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
Page 1. Using Combinational Verification for Sequential Circuits Rajeev K. Ranjan Vigyan Singhal ... more Page 1. Using Combinational Verification for Sequential Circuits Rajeev K. Ranjan Vigyan Singhal Fabio Somenzi Robert K. Brayton [email protected][email protected][email protected][email protected] Synopsys Inc. ...
Implicit state enumeration for extended finite state machines relies on a decision procedure for ... more Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the experiments we performed.
The breadth-first manipulation technique has proven effective in dealing with very large sized BD... more The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, till now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of this work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, we propose techniques to handle the computational and memory overheads. We feel that com ordering with the powerful manipul a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The effiy of the proposed techniques is demonstrated on a
International Conference on Computer Aided Design, 1998
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of... more Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a decade, its exact optimization capability has not been formally established. We show that retiming and resynthesis can exactly implement 1-step equivalent state transition graph transformations. This result is the strongest to date. We also show how the notions of retiming and resynthesis can be moderately extended to achieve more powerful state transition graph transformations. Our work will provide theoretical foundation for practical retiming and resynthesis based optimization and verification.
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Raje... more ... We also discuss how what-if capability enables traceless debugging. 6. REFERENCES [1]Rajeev Ranjan et al. 2009. Toward harnessing the true potential of IP reuse. Design Con 2009. [2] Jamil Mazzawi et al. 2008. Formal technology in the post-silicon lab. ...
Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on... more Abstract The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using ...
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