Papers by prafulla d Gawande
Design Approach towards High Performance Memory of 6 Transistors SRAM Cell Using 45nm CMOS Technology
Semiconductor memory arrays capable of storing large quantities of digital information are essent... more Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in a particular system depends on the type of application, but, in general, the number of transistors utilized for the information (data) storage function is much larger than the number of transistors used in logic operations and for other purposes. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development towards more compact design rules and, consequently, toward higher data storage densities. The trend towards higher memory density and larger storage capacity will continue to push the leading edge of digital system design. The Microwind 3.1 software will allow designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. Th...
A pseudo random number generator (PRNG), also known as a deterministic random bit generator(DRBG)... more A pseudo random number generator (PRNG), also known as a deterministic random bit generator(DRBG), is an algorithm for generating a sequence of random numbers. This paper presents an implementation of pseudo random number generator. The design has been specified in VHDL and is implemented on altera FPGA device. It is based on the Residue Number System (RNS),which gives us the way to design a very fast circuit. This paper presents design and implementation of a pseudo-random number generator based on Blum Blum Shub, XOR Shift, Fibonacci series and Galois LFSR methods. We will demonstrate that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design will specify in VHDL and will analyze on altera FPGA parameter. Which will give us higher throughput and also the parameter like area, propagation delay and
Design of High Speed Addressable Memory based on Memory-Resistance Using 45nm
The amount of memory required in a particular system depends on the type of application, but, in ... more The amount of memory required in a particular system depends on the type of application, but, in general, the number of transistors utilized for the information (data) storage function is much larger than the number of transistors used in logic operations and for other purposes. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development towards more compact design rules and, consequently, toward higher data storage densities. The trend towards higher memory density and larger storage capacity will continue to push the leading edge of digital system design. Content addressable memory (CAM) having large capacity is a key element in wide variety of applications. A major challenge in realization of such systems is the complexities structure of scaling MOS transistors. This paper provides a new approach towards the layout design and modeling of memristor based CAM (MCAM) using a combination of MOS devices to form a core of a m...
IOSR Journal of Electrical and Electronics Engineering, 2012
In data communication the codes are used to for security and effectiveness which is thoroughly fo... more In data communication the codes are used to for security and effectiveness which is thoroughly followed by the network. Here in LBC (linear block code), COC (convolution code), Concatenated codes (CC) are used. The work presented here is used the to make comparative effectiveness of this codes in order to make secure data analysis. Error coding is a method of detecting and correcting these errors to ensure information is transferred intact from its source to destination. Error coding uses mathematical formulas to encode data bits at the source into longer bit words for is transmission. Decoding of the code word is possible at side of receiver. The extra bits in the code word provide redundant bit, according to the coding scheme used, will allow the destination to use the decoding process to determine if the communication mediums expected error rate, signal to noise ratio and whether or not data retransmission is possible. Above coding technique implemented system can show error of exact bit in given data this error display bitwise. Faster processors and better communications technology make more complex coding schemes, with better error detecting and correcting capabilities, possible for smaller embedded systems, allowing for more robust communications.
ijmra.us
During digital data transmission in digital communication system, noise is added and physical def... more During digital data transmission in digital communication system, noise is added and physical defects in the communication medium can cause random errors during data transmission. Error coding is a method of detecting and correcting these errors to ensure information is transferred intact from its source to destination. Error coding is used for fault tolerant computing in computer memory, magnetic and optical data storage media, satellite and deep space communications, network communications, cellular telephone networks, and almost any other form of digital data communication. Error coding uses mathematical formulas to encode data bits at the source into longer bit words for is transmission. Decoding of the code word is possible at side of receiver. The extra bits in the code word provide redundant bit, according to the coding scheme used, will allow the destination to use the decoding process to determine if the communication medium's expected error rate, signal to noise ratio and whether or not data retransmission is possible. Faster processors and better communications technology make more complex coding schemes, with better error detecting and correcting capabilities, possible for smaller embedded systems, allowing for more robust communications. The proposed title discloses a novel approach for detection and correction of binary stream transmission errors such as random errors and bursts errors in digital communication systems. The fault detection and correction will be accomplished by Linear Block Code, Convolution Code or concatenated Code Error-Control Coding techniques.
Optimal performance of convolution coded OFDM
2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016
OFDM is the next generation transmission technique for high bit-rate communication systems. OFDM ... more OFDM is the next generation transmission technique for high bit-rate communication systems. OFDM has suffered by peak-to-average power ratio (PAPR), it is one of the major disadvantages of OFDM. In this paper, Convolution code is applied to minimize the peak-to-average power ratio (PAPR) and BER of Orthogonal Frequency Division Multiplexing (OFDM) system, and had investigated effect of convolution code on PAPR and BER. We also proposed method to find optimal values of Eb/No for minimum PAPR and BER based on the tradeoff between the number of assigned subcarriers, order of modulation and coding rate. Simulation result shows that the proposed method had effectively obtained the minimum PAPR and BER with convolution code at optimal value of Eb/No for MIMO OFDM channel.
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Papers by prafulla d Gawande