Papers by marcos antonio martinez peiro
Seventh International Symposium on Signal Processing and Its Applications, 2003. Proceedings., 2003
Page 1. A NEW INVERSE DISCRETE WAVELET PACKET TRANSFORM ARCHITECTURE Guillermo Pay&am... more Page 1. A NEW INVERSE DISCRETE WAVELET PACKET TRANSFORM ARCHITECTURE Guillermo Pay&, Marcos M. Peird, Francisco J. Ballester, Vicente Herrero and Joaquin Cerdd Digital System Design Group. Universidad Politecnica de Valencia. SPAIN. ...
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
A Two Dimensions Discrete Cosine Transform implementation on FPGA, using polynomial transformatio... more A Two Dimensions Discrete Cosine Transform implementation on FPGA, using polynomial transformation algorithm on two dimensions is presented. The precision and area results are reported to be compared with the classical Row-Column implementation. Advantages and drawbacks are commented. Since One Dimension DCT is a basic block for the implementation of Two Dimensions, we first show two 1D-DCT Implementations to be selected for use on 2D. A modification to the polynomial transform is also shown in order to get a normalized 2D-DCT. All the designs are synthesized and implemented on Xilinx Virtex FPGAs.
Sensors (Basel, Switzerland), Jan 12, 2018
Pluvial flash floods in urban areas are becoming increasingly frequent due to climate change and ... more Pluvial flash floods in urban areas are becoming increasingly frequent due to climate change and human actions, negatively impacting the life, work, production and infrastructure of a population. Pluvial flooding occurs when intense rainfall overflows the limits of urban drainage and water accumulation causes hazardous flash floods. Although flash floods are hard to predict given their rapid formation, Early Warning Systems (EWS) are used to minimize casualties. We performed a systematic review to define the basic structure of an EWS for rain flash floods. The structure of the review is as follows: first, Section 2 describes the most important factors that affect the intensity of pluvial flash floods during rainfall events. Section 3 defines the key elements and actors involved in an effective EWS. Section 4 reviews different EWS architectures for pluvial flash floods implemented worldwide. It was identified that the reviewed projects did not follow guidelines to design early warnin...
Lecture Notes in Computer Science, 2004
This work describes a Virtex-II implementation of a custom DSP for QRS-Complex detection, ECG sig... more This work describes a Virtex-II implementation of a custom DSP for QRS-Complex detection, ECG signal analysis and data compression for optimum transmission and storage. For QRS-Complex detection we introduce a custom architecture based on a modification of the Hamilton-Tompkins (HT) algorithm oriented to area saving. We also use biorthogonal wavelet transform for ECG signal compression and main ECG parameters estimation.
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)
ABSTRACT The use of the offset binary code (OBC) together with distributed arithmetic (DA) has be... more ABSTRACT The use of the offset binary code (OBC) together with distributed arithmetic (DA) has been addressed by several authors as an area-efficient method to implement VLSI systems. In this paper is shown that it is not as efficient as if it is implemented on a FPGA. To verify that conclusion, two sets of digit-serial complex multipliers have been designed and implemented on FPGA. The first ones are only based on the DA technique and the second on OBC and DA. The results show that the first ones achieve better performance than the others and are more area-time efficient
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
In this paper we discuss the design and implementation of a highspeed FIR filter for both interpo... more In this paper we discuss the design and implementation of a highspeed FIR filter for both interpolation and decimation of the sample frequency. Several FIR filter structures are compared and various schemes for simplifying the implementation of the multiplications are evaluated. Carry-save adders with carryoverflow correction are used in the implementation. The results in terms of chip area and power consumption are compared using a standard 0.8 µm 3.3 V CMOS process.
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)
In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional dig... more In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional digit-serial/parallel multipliers and their pipelined versions are presented. Every structure has been implemented on FPGA and the results are given. These results have been analysed and it is detected that the pipelined ones do not have the throughput improvement expected because of a logic depth increment. As a consequence, a new structure based on the fast serial/parallel multiplier proposed in [1] has been developed. The new multipliers designed achieve better performance than the previous ones: their throughput is higher than it in the pipelined serial/parallel multipliers with nearly the same cost in area.
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)
Field Programmable Logic and Application, 2003
... 533–542, 2003.  Springer-Verlag Berlin Heidelberg 2003 Fully Parameterized Discrete Wavelet ... more ... 533–542, 2003.  Springer-Verlag Berlin Heidelberg 2003 Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA Guillermo Payá, Marcos M. Peiró, Francisco Ballester, and Francisco Mora Universidad Politécnica de Valencia. ...
VLSI Circuits and Systems III, 2007
As today's video applications are being requested in many portable end-user devices, and the... more As today's video applications are being requested in many portable end-user devices, and these ones are far capable of holding and processing large amounts of video data, there is a need for bit rate improvement in compression algorithms. The objective of this paper is to propose a hardware based post-compression enhancer situated between the Video Coding Layer and the Network Abstraction Layer of H.264. Our research analyzes the resulting bit streams produced by the emerging H.264 standard. The goal is to enhance compression rates by proposing simple post-compression techniques based in symbol's statistics. The CABAC and CAVLC entropy coders used in H.264 work optimally for 1-bit symbols, and the statistical distribution among them is almost the best. Our studies reveal that the bit streams presents similar results for 8-bit symbols, and thus a post-compression using well known byte-based mechanisms will not yield better results; further more, our studies also show that they even degrade the original compression rate. Nevertheless, a non equally distribution using 6-bits symbols in 2046-bits discrete data packets is found, which can be exploited to boost compression. This distribution varies between 5.4% for the most probable symbol and 0.98% for the least probable symbol in average. Again, simple coding a few of the most probable symbols will result in bit rate reduction. A 1- bit compression enhanced used flag penalty must be introduced for each discrete packet, increasing its size in 0.049%.
SPIE Proceedings, 2003
The present article describes a new high-efficient architecture for 1-D discrete wavelet packet t... more The present article describes a new high-efficient architecture for 1-D discrete wavelet packet transform (DWPT) base on lifting, folded and pipeline techniques, which makes possible to expand three completes levels. An architecture for a CDF (2, 2) wavelet base ...
Microprocessors and Microsystems, 2008
This paper presents an improved accelerator core for H.264/AVC video-coding motion estimation. Th... more This paper presents an improved accelerator core for H.264/AVC video-coding motion estimation. The proposed hardware architecture meets the integer-pixel, full-search block-matching algorithm requirements with an optimal memory management and an effective data-path. Performance characteristics like low latency, high processing speed and efficiency near 100% are achieved without a high control overhead. The core calculates the 41 best motion vectors using
IEEE Transactions on Education, 2006
Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
Page 1. Architectures for ICT on FPGA Arturo Mendez Patifio, Marcos A. Martinez Peiro,Francisco B... more Page 1. Architectures for ICT on FPGA Arturo Mendez Patifio, Marcos A. Martinez Peiro,Francisco Ballester, G. Paya Instituto Tecnoldgico de Morelia (Me&#x27;xico), Universidad Polite&#x27;cnicu de Valencia (Espuiiu) mpeiro@,eln.upv.es Abstract ...
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Papers by marcos antonio martinez peiro