Journal of emerging technologies and innovative research, 2018
This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Ampl... more This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Amplifier using gpdk 0.18μM CMOS technology. The proposed op-amp consists of pair of NMOS transistors as an input differential gain stage, the NMOS differential pair is chosen for low power consumption and also to maintain good UGF. The design is simulated using cadence spectre simulator, under ±1V supply voltage. The proposed design shows 68.6dB gain, Phase margin of 50 0 , UGF of 13.1MHz, with power consumption of 30μW. IndexTerms—Folded Cascode Operational Amplifier, Op-Amp, 180nM CMOS Op-Amp.
International Journal for Research in Applied Science and Engineering Technology, 2019
This paper presents the design of low voltage low power 10T full adder with minimum leakage power... more This paper presents the design of low voltage low power 10T full adder with minimum leakage power, and its transient analysis with cadence tools. Adder is the basic building block of Arithmetic in digital circuits, the area and power consumption of adder plays a vital role in portable devices. The low voltage low power full adder circuits are widely used in portable applications as it improves the battery lifetime. In this paper we have presented the design, simulation and comparative analysis of 27T and 10T full adder topologies with various supply voltages and lower technology node at Cadence Virtuoso TSMC 16nM technology.
Journal of emerging technologies and innovative research, 2018
This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Ampl... more This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Amplifier using gpdk 0.18μM CMOS technology. The proposed op-amp consists of pair of NMOS transistors as an input differential gain stage, the NMOS differential pair is chosen for low power consumption and also to maintain good UGF. The design is simulated using cadence spectre simulator, under ±1V supply voltage. The proposed design shows 68.6dB gain, Phase margin of 50 0 , UGF of 13.1MHz, with power consumption of 30μW. IndexTerms—Folded Cascode Operational Amplifier, Op-Amp, 180nM CMOS Op-Amp.
International Journal for Research in Applied Science and Engineering Technology, 2019
This paper presents the design of low voltage low power 10T full adder with minimum leakage power... more This paper presents the design of low voltage low power 10T full adder with minimum leakage power, and its transient analysis with cadence tools. Adder is the basic building block of Arithmetic in digital circuits, the area and power consumption of adder plays a vital role in portable devices. The low voltage low power full adder circuits are widely used in portable applications as it improves the battery lifetime. In this paper we have presented the design, simulation and comparative analysis of 27T and 10T full adder topologies with various supply voltages and lower technology node at Cadence Virtuoso TSMC 16nM technology.
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Papers by kamal vijetha