kalamani c

Test data compression using a hybrid of bitmask dictionary and 2n pattern runlength coding methods

WASET, 2015

In VLSI, testing plays an important role. Major problem in testing are test data volume and test ... more In VLSI, testing plays an important role. Major problem in testing are test data volume and test power. The important solution to reduce test data volume and test time is test data compression. The Proposed technique combines the bit maskdictionary and 2 n pattern run length-coding method and provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. This method has been implemented using Mat lab and HDL Language to reduce test data volume and memory requirements. This method is applied on various benchmark test sets and compared the results with other existing methods. The proposed technique can achieve a compression ratio up to 86%.

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Survey of Low Power Testing Using Compression Techniques

International Journal of Electronics & Communication Technology , 2013

Power consumption of very large scale circuits may increase significantly during testing. This ex... more Power consumption of very large scale circuits may increase significantly during testing. This extra power consumption may give rise to several problems. It may be responsible for cost, performance verification, technology related problems and can reduce the battery life when on-line testing is considered. Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in the literatures. Test data compression is an effective methodology for reducing test data volume and testing time. The survey of the low power testing using compression techniques that can be used to test VLSI circuits by combining better performance of these methods.

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Secured mutual authentication protocol for radio frequency identification systems

WASET, 2020

Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to trac... more Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to track the objects. This technology transmits signals between tag and reader to fetch information from the tag with a unique serial identity. Generally, the drawbacks of RFID technology are high cost, high consumption of power and weak authentication systems between a reader and a tag. The proposed protocol utilizes less dynamic power using reversible truncated multipliers which are implemented in RFID tag-reader with mutual authentication protocol system to reduce both leakage and dynamic power consumption. The proposed system was simulated using Xilinx and Cadence tools.

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Design and implementation of 4 bit multiplier using fault tolerant hybrid full adder

WASET, 2017

The fault tolerant system plays a crucial role in the critical applications which are being used ... more The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

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A Modified Run Length Coding Technique for Test Data Compression Based on Multi-Level Selective Huffman Coding

WASET, 2017

Test data compression is an efficient method for reducing the test application cost. The problem ... more Test data compression is an efficient method for reducing the test application cost. The problem of reducing test data has been addressed by researchers in three different aspects: Test Data Compression, Built-in-Self-Test (BIST) and Test set compaction. The latter two methods are capable of enhancing fault coverage with cost of hardware overhead. The drawback of the conventional methods is that they are capable of reducing the test storage and test power but when test data have redundant length of runs, no additional compression method is followed. This paper presents a modified Run Length Coding (RLC) technique with Multilevel Selective Huffman Coding (MLSHC) technique to reduce test data volume, test pattern delivery time and power dissipation in scan test applications where redundant length of runs is encountered then the preceding run symbol is replaced with tiny codeword. Experimental results show that the presented method not only improves the test data compression but also reduces the overall test data volume compared to recent schemes. Experiments for the six largest ISCAS-98 benchmarks show that our method outperforms most known techniques. Keywords-Modified run length coding, multilevel selective Huffman coding, built-in-self-test modified selective Huffman coding, automatic test equipment.

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Microprocessors and Microsystems

ELSEVIER, 2020

Main disputes of digital integrated circuits testing are increasing test data volume and test pow... more Main disputes of digital integrated circuits testing are increasing test data volume and test power. The proposed encoding schemes are a combination of nine coded and selective pattern compression, Alternate Variable Run length code to reduce test data volume. The test cubes are divided into multiples of 8, 16, 32, and 64 blocks to upsurge the relationship among the successive test patterns which offers enriched test data reduction. The test data blocks are encoded with two methods in order to reduce test data volume. In the first method, the test sets are encoded using nine coded with selective pattern coding to expand the test data density. In the second method, the test sets are encoded using nine coded with Alternate variable run length laterally with selective pattern coding to improve the test data compression. Investigational results show that the proposed first and second approaches offer a maximum of 76% and 83% of compression ratio respectively for ISCAS'89 benchmark circuits.

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Microprocessors and Microsystems

ELSEVIER, 2019

The RFICs plays an important role in wireless communication systems due to their effective operat... more The RFICs plays an important role in wireless communication systems due to their effective operation in the 2.4 GHz frequency, popularly known as ISM (Industrial, Scientific and Medical) band. LNA and Mixers are the major components used in transceivers for the purpose of amplification and frequency translation. Such LNAs and mixers are of different kinds and various techniques are used for their optimization. The paper describes the design of a differential LNA with two single stranded source degenerate LNAs with greater increase in gain. differential LNA is combined with Double balanced mixer with a current mirror circuit and BALUN with the bias controlling MOSFETs are used to show the better performance at 2.4 GHz frequency range. CMOS has become a viable technology for the design of high-performance receivers in the Radio Frequency (RF) regime. The conversion gain of 22.28 dB and IF of 595 MHz of Differential LNA with Double Balanced mixer are higher than the cross comparison results of the other methods at 180 nm technology. CMOS implementation of the design is done using the Cadence Virtuoso tool of 180 nm technology at 2.4 GHz frequency and 1.8 V of supply voltage.

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A Combined Compatible Block Coding and Run Length Coding Techniques for Test Data Compression

Higher Circuit Densities in system-on-chip (SOC) designs and increase in design complexity have l... more Higher Circuit Densities in system-on-chip (SOC) designs and increase in design complexity have led to drastic increase in test data volume. This results in long test application time and high tester memory requirement. Test Data Compression/Decompression addresses this problem by reducing the test data volume without affecting the overall system performance. This paper proposes a test data compression scheme that combines the advantages of compatible block coding followed by simple run lengthcoding techniques to address the large test data volume of Automatic Test Equipment. This test data compression technique significantly reduces memory requirements. The algorithm is applied on various benchmark circuits and compared results with existing test compression/Decompression techniques. The experimental evaluation revealed that the proposed method achieves on an average, a compression ratio of 70%. The proposed approach, improves the compression efficiency without introducing any additional decompression penalty. Experimental results demonstrate that this approach produces up to 30% better compression compared to existing methods.

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Secured mutual authentication protocol for radio frequency identification systems

Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to trac... more Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to track the objects. This technology transmits signals between tag and reader to fetch information from the tag with a unique serial identity. Generally, the drawbacks of RFID technology are high cost, high consumption of power and weak authentication systems between a reader and a tag. The proposed protocol utilizes less dynamic power using reversible truncated multipliers which are implemented in RFID tag-reader with mutual authentication protocol system to reduce both leakage and dynamic power consumption. The proposed system was simulated using Xilinx and Cadence tools.

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Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder

The fault tolerant system plays a crucial role in the critical applications which are being used ... more The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Download

A modified run length coding technique for test data compression based on multi level selective huffman coding

Test data compression is an efficient method for reducing the test application cost. The problem ... more Test data compression is an efficient method for reducing the test application cost. The problem of reducing test data has been addressed by researchers in three different aspects: Test Data Compression, Built-in-Self-Test (BIST) and Test set compaction. The latter two methods are capable of enhancing fault coverage with cost of hardware overhead. The drawback of the conventional methods is that they are capable of reducing the test storage and test power but when test data have redundant length of runs, no additional compression method is followed. This paper presents a modified Run Length Coding (RLC) technique with Multilevel Selective Huffman Coding (MLSHC) technique to reduce test data volume, test pattern delivery time and power dissipation in scan test applications where redundant length of runs is encountered then the preceding run symbol is replaced with tiny codeword. Experimental results show that the presented method not only improves the test data compression but also reduces the overall test data volume compared to recent schemes. Experiments for the six largest ISCAS-98 benchmarks show that our method outperforms most known techniques. Keywords-Modified run length coding, multilevel selective Huffman coding, built-in-self-test modified selective Huffman coding, automatic test equipment.

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Survey of Low Power Testing Using Compression Techniques

Power consumption of very large scale circuits may increase significantly during testing. This ex... more Power consumption of very large scale circuits may increase significantly during testing. This extra power consumption may give rise to several problems. It may be responsible for cost, performance verification, technology related problems and can reduce the battery life when on-line testing is considered. Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in the literatures. Test data compression is an effective methodology for reducing test data volume and testing time. The survey of the low power testing using compression techniques that can be used to test VLSI circuits by combining better performance of these methods.

Download

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