Papers by bouthaina dammak
Microprocessors and Microsystems, Nov 1, 2015
Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well... more Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well as dedicated accelerators in the same chip. These Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures will allow the design of very complex System-on-Chips (SoC) on a single FPGA chip and will fulfill modern application requirements, in terms of performance/energy consumption ratio. In this paper, we extend existing FPGA-based Ht-MPSoC architectures by considering sharing hardware accelerators among the cores. In these architectures, cores on the FPGA may have different resources that can be shared in different manners. To explore the large space of possible configurations of Ht-MPSoC on FPGA, designer needs a fast and accurate exploration tool. For this reason, a Mixed Integer Programming (MIP) model is also proposed to determine the Ht-MPSoC configuration that consumes the least HW resources while respecting the application execution time constraints. Using our MIP model, the design space of several hundreds of private and shared HW accelerators can be explored in a reasonable time with high accuracy.
A Private Smart parking solution based on Blockchain and AI
NFT-IoT Pharma Chain : IoT Drug traceability system based on Blockchain and Non Fungible Tokens (NFTs)
Journal of King Saud University - Computer and Information Sciences
A Private Smart parking solution based on Blockchain and AI
2022 15th International Conference on Security of Information and Networks (SIN)
The Journal of Supercomputing
In this article, Fairouz Fakhfakh was incorrectly denoted as the corresponding author, but it sho... more In this article, Fairouz Fakhfakh was incorrectly denoted as the corresponding author, but it should have been Bouthaina Dammak. The original article has been corrected. Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Multi-objective approach for scheduling time-aware business processes in cloud-fog environment
The Journal of Supercomputing
From Dynamic UML/MARTE Models to Early Schedulability Analysis of RTES with Dependent Tasks
The process of verifying whether Real-Time Embedded Systems (RTES) meet their temporal requiremen... more The process of verifying whether Real-Time Embedded Systems (RTES) meet their temporal requirements is a major step during the system design. This step, called schedulability analysis, must be carried out at early design stages to avoid system failures. Currently, researchers are interested in using high-level techniques to raise the abstraction level and reduce the designers’ effort. Nevertheless, only the scheduling approaches that prohibit task migration have been supported. An attempt to consider semi-partitioned and global scheduling approaches, which allow task migration, has been recently proposed. However, it doesn’t support dependent tasks. In this context, this paper proposes an automatic process for early schedulability analysis considering dependent tasks and scheduling approaches with task migration. The focus is on the transformation of dynamic models annotated through the Unified Modeling Language (UML) profile for Modeling and Analysis of Real-Time Embedded systems (...
IEEE Embedded Systems Letters, 2015
Using application-specific instructions for Heterogeneous MPSoC allows to find a good performance... more Using application-specific instructions for Heterogeneous MPSoC allows to find a good performance/energy tradeoff. For MPSoC architecture executing different multimedia applications, we expect a large number of potential custom instructions. In order to explore the potential of all these instructions, we propose to identify the similar critical computations to be executed on hardware accelerators (HWA) shared between processors. Depending on the running applications in one side and their needs in performance and area usage on the other side, private and shared hardware accelerators are attached to the different cores. This leads to a large architectural space exploration. In this paper we propose an FPGA-based framework capable of identifying the configuration of HWA targeted to an MPSoC architecture. Our framework incorporates a hardware accelerators sharing methodology to optimize area/performance trade-off. The comparison of framework-estimated results and real measurements proves the efficiency of our framework.
Microprocessors and Microsystems, 2015
Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well... more Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well as dedicated accelerators in the same chip. These Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures will allow the design of very complex System-on-Chips (SoC) on a single FPGA chip and will fulfill modern application requirements, in terms of performance/energy consumption ratio. In this paper, we extend existing FPGA-based Ht-MPSoC architectures by considering sharing hardware accelerators among the cores. In these architectures, cores on the FPGA may have different resources that can be shared in different manners. To explore the large space of possible configurations of Ht-MPSoC on FPGA, designer needs a fast and accurate exploration tool. For this reason, a Mixed Integer Programming (MIP) model is also proposed to determine the Ht-MPSoC configuration that consumes the least HW resources while respecting the application execution time constraints. Using our MIP model, the design space of several hundreds of private and shared HW accelerators can be explored in a reasonable time with high accuracy.
Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC
2014 17th Euromicro Conference on Digital System Design, 2014
ABSTRACT Modern FPGA allows the design of very complex System-on-Chips (SoC). To fulfil modern ap... more ABSTRACT Modern FPGA allows the design of very complex System-on-Chips (SoC). To fulfil modern application require- ments, in terms of performance/energy consumption ratio, Het- erogeneous Multiprocessor System-on-Chip (Ht- MPSoC) archi- tectures represent a promising solution. In such systems, the processor instruction set is enhanced by application-specific cus- tom instructions implemented on reconfigurable fabrics, namely FPGA. To increase area utilization and guarantee application constraint respect, we propose a new Ht-MPSoC architecture where hardware accelerators (HW accelerators) are shared among different processors in an intelligent manner. In this paper, we extend existing Ht-MPSoC architectures by considering asym- metric (AHt-MPSoC). In these architectures, cores have different resources that may share in different manners. Depending on the running applications and their needs in processing, private and shared HW accelerators are attached to the different cores. On a 8-core AHt-MPSoC we obtained a speed of 2.6 with a reduced number of HW accelerators for our benchmarks.
Sensors, 2022
Over the past several years, the adoption of HealthCare Monitoring Systems (HCS) in health center... more Over the past several years, the adoption of HealthCare Monitoring Systems (HCS) in health centers and organizations like hospitals or eldery homes growth significantly. The adoption of such systems is revolutionized by a propelling advancements in IoT and Blockchain technologies. Owing to technological advancement in IoT sensors market, innovations in HCS to monitor patients health status have motivated many countries to strength their efforts to support their citizens with such care delivery systems under the directives of a physician who has access to patient’s data. Nevertheless, secure data sharing is a principal patient’s concern to be comfort to use such systems. Current HCS are not able to provide reassuring security policies. For that, one of our focus in this work, is to provide security countermeasures, likewise cost-efficient solution for HCS by integrating storage model based on Blockchain and Interplanetary File Systems (IPFS). Blockchain technology is an emerging solu...
Electric Power Systems Research, 2013
This paper presents a mixed-integer linear programming approach to solving the problem of optimal... more This paper presents a mixed-integer linear programming approach to solving the problem of optimal type, size and allocation of distributed generators (DGs) in radial distribution systems. In the proposed formulation, (a) the steady-state operation of the radial distribution system, considering different load levels, is modeled through linear expressions; (b) different types of DGs are represented by their capability curves; (c) the short-circuit current capacity of the circuits is modeled through linear expressions; and (d) different topologies of the radial distribution system are considered. The objective function minimizes the annualized investment and operation costs. The use of a mixed-integer linear formulation guarantees convergence to optimality using existing optimization software. The results of one test system are presented in order to show the accuracy as well as the efficiency of the proposed solution technique.
Soft-core reduction methodology for SIMD architecture: OPENRISC case study
2010 5th International Design and Test Workshop, 2010
Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the incre... more Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.
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Papers by bouthaina dammak