The need for devices that consume minimum amount of power was a major driving force behind the de... more The need for devices that consume minimum amount of power was a major driving force behind the development of CMOS technologies. Reduction of power consumption makes a device more reliable. As a result, CMOS devices are best known for low power consumption. Most research on the power consumption of circuits has been focused on the switching power and the power dissipated by the leakage current has been comparatively minor area. Today, every designer either analog circuit or a digital circuit designer is concerned about the amount of power consumption in the circuit at the end. Multi-threshold CMOS is becoming a trendy circuit design technique for low power, high performance application. The paper briefs the implementation of a novel CMOS 8 bit Vedic Multiplier using MTCMOS. General Terms PTL (pass transistor logic), Low power, Multiplier.
International Journal of Computer Applications, Jul 18, 2014
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various ... more Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers. .
The need for devices that consume minimum amount of power was a major driving force behind the de... more The need for devices that consume minimum amount of power was a major driving force behind the development of CMOS technologies. Reduction of power consumption makes a device more reliable. As a result, CMOS devices are best known for low power consumption. Most research on the power consumption of circuits has been focused on the switching power and the power dissipated by the leakage current has been comparatively minor area. Today, every designer either analog circuit or a digital circuit designer is concerned about the amount of power consumption in the circuit at the end. Multi-threshold CMOS is becoming a trendy circuit design technique for low power, high performance application. The paper briefs the implementation of a novel CMOS 8 bit Vedic Multiplier using MTCMOS. General Terms PTL (pass transistor logic), Low power, Multiplier.
International Journal of Computer Applications, Jul 18, 2014
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various ... more Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers. .
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