Papers by Wouter Vlothuizen
Bulletin of the American Physical Society, Mar 18, 2021
21st European Signal Processing Conference (EUSIPCO 2013), 2013
A lightweight radar system, suitable for use on board small airborne platforms, has been built an... more A lightweight radar system, suitable for use on board small airborne platforms, has been built and tested. The radar system comprises a digital receive array, offering full beam forming flexibility at the cost of high data rates and heavy processing loads. In this paper, the requirements and architecture for multi-channel SAR processing are discussed and processing results from recent airborne campaigns are presented.
2016 European Radar Conference (EuRAD), 2016
The AMBER multichannel FMCW SAR enables novel SAR and GMT modes, such as simultaneous Strip and S... more The AMBER multichannel FMCW SAR enables novel SAR and GMT modes, such as simultaneous Strip and Spot imaging. To enable such advanced modes in an airborne processor for small aircraft, a high performance and power efficient computing solution is required. Multi-channel SAR processing by means of back projection has been implemented on several GPU platforms, and performance tests have been performed. The results indicate that real-time solutions with state-of-the art GPUs are feasible.
Physical Review Letters, 2021
We introduce the sudden variant (SNZ) of the Net Zero scheme realizing controlled-Z (CZ) gates by... more We introduce the sudden variant (SNZ) of the Net Zero scheme realizing controlled-Z (CZ) gates by baseband flux control of transmon frequency. SNZ CZ gates operate at the speed limit of transverse coupling between computational and non-computational states by maximizing intermediate leakage. The key advantage of SNZ is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. We realize SNZ CZ gates in a multitransmon processor, achieving 99.93 ± 0.24% fidelity and 0.10 ± 0.02% leakage. SNZ is compatible with scalable schemes for quantum error correction and adaptable to generalized conditional-phase gates useful in intermediate-scale applications.
2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2019
A widely-used quantum programming paradigm comprises of both the data ow and control ow. Existing... more A widely-used quantum programming paradigm comprises of both the data ow and control ow. Existing quantum hardware cannot well support the control ow, signi cantly limiting the range of quantum so ware executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive ow control on the hardware. Also, as observed with the quantum microinstruction set MIS [1], the quantum instruction set architecture (QISA) design may su er from limited scalability and exibility because of microarchitectural constraints. It is an open challenge to design a scalable and exible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program ow control, and is executed on a quantum control microarchitecture. With e cient timing speci cation, single-operation-multiple-qubit execution, and a very-long-instruction-word architecture, eQASM presents better scalability than MIS. e de nition of eQASM focuses on the assembly level to be expressive. antum operations are congured at compile time instead of being de ned at QISA design time. We instantiate eQASM into a 32-bit instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor.
Future fault-tolerant quantum computers will require storing and processing quantum data in logic... more Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. We realize a suite of logical operations on a distance-two logical qubit stabilized using repeated error detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere, and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference through detailed characterization. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.
Bulletin of the American Physical Society, Mar 5, 2015
2011 International Conference on Parallel Processing, 2011
Application development for many-core processors is predominately hardware-centric: programmers d... more Application development for many-core processors is predominately hardware-centric: programmers design, implement, and optimize applications for a pre-chosen target platform. While this approach may deliver very good performance, it lacks portability, being inefficient for applications that aim to use multiple architectures or large-scale parallel platforms with heterogeneous many-core nodes. In this work, we focus on application portability. Therefore, we propose an applicationcentric approach for developing parallel workloads for manycores, and we make use of OpenCL to preserve portability until the very last optimization stages. We validate our applicationcentric approach using 3D bodyscan, a data intensive application with soft real-time constraints. Thus, we design and implement OCL-bodyscan (the portable OpenCL-based version of 3D Bodyscan), and we evaluate its performance on three families of platforms-general purpose multi-cores, graphical processing units, and the Cell/B.E.. Our experiments show that our application-centric strategy enables portability and leads to good performance results. Additionally, typical platform-specific optimizations can be applied in the final implementation stages, leading to performance results similar to those obtained using the native tool-chains.
2009 IEEE Radar Conference, 2009
This paper presents a brute force method to perform real-time SAR processing. The method has seve... more This paper presents a brute force method to perform real-time SAR processing. The method has several advantages over traditional so-called fast SAR implementations, as it does not make any approximations to alleviate the processing burden. However, the method does allow efficient implementation on multi-core platforms. It is implemented on a Cell processor and achieves better quality at roughly twice the speed required for real-time operation (better than real-time). A patent is submitted and pending approval.
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Papers by Wouter Vlothuizen