TREXIO is an open-source file format and library developed for the storage and manipulation of da... more TREXIO is an open-source file format and library developed for the storage and manipulation of data produced by quantum chemistry calculations. It is designed with the goal of providing a reliable and efficient method of storing and exchanging wave function parameters and matrix elements, making it an important tool for researchers in the field of quantum chemistry. In this work, we present an overview of the TREXIO file format and library. The library consists of a front-end implemented in the C programming language and two different back-ends: a text back-end and a binary back-end utilizing the HDF5 library which enables fast read and write operations. It is compatible with a variety of platforms and has interfaces for the Fortran, Python, and OCaml programming languages. In addition, a suite of tools has been developed to facilitate the use of the TREXIO format and library, including converters for popular quantum chemistry codes and utilities for validating and manipulating data stored in TREXIO files. The simplicity, versatility, and ease of use of TREXIO make it a valuable resource for researchers working with quantum chemistry data.
HAL (Le Centre pour la Communication Scientifique Directe), 2008
A number of computational applications lack instruction-level parallelism. This loss is particula... more A number of computational applications lack instruction-level parallelism. This loss is particularly acute on sequences of dependent instructions on wide-issue or deeply pipelined architectures. We consider four real applications from computational biology, cryptanalysis, and data compression. These applications are characterized by long sequences of dependent instructions, irregular control-flow and intricate scalar and memory dependence patterns. While these benchmarks exhibit good memory locality and branch-predictability, state-of-the-art compiler optimizations fail to exploit much instruction-level parallelism. This paper shows that major performance gains are possible on such applications, through a loop transformation called deep jam. This transformation reshapes the control-flow of a program to facilitate the extraction of independent computations through classical back-end techniques. Deep jam combines accurate dependence analysis and control speculation, with a generalized form of recursive, multi-variant unroll-and-jam; it brings together independent instructions across irregular control structures, removing memory-based dependences through scalar and array renaming. This optimization contributes to the extraction of fine-grain parallelism in irregular applications. We propose a feedback-directed deep jam algorithm, selecting a jamming strategy, function of the architecture and application characteristics.
HAL (Le Centre pour la Communication Scientifique Directe), 2008
A number of computational applications lack instruction-level parallelism. This loss is particula... more A number of computational applications lack instruction-level parallelism. This loss is particularly acute on sequences of dependent instructions on wide-issue or deeply pipelined architectures. We consider four real applications from computational biology, cryptanalysis, and data compression. These applications are characterized by long sequences of dependent instructions, irregular control-flow and intricate scalar and memory dependence patterns. While these benchmarks exhibit good memory locality and branch-predictability, state-of-the-art compiler optimizations fail to exploit much instruction-level parallelism. This paper shows that major performance gains are possible on such applications, through a loop transformation called deep jam. This transformation reshapes the control-flow of a program to facilitate the extraction of independent computations through classical back-end techniques. Deep jam combines accurate dependence analysis and control speculation, with a generalized form of recursive, multi-variant unroll-and-jam; it brings together independent instructions across irregular control structures, removing memory-based dependences through scalar and array renaming. This optimization contributes to the extraction of fine-grain parallelism in irregular applications. We propose a feedback-directed deep jam algorithm, selecting a jamming strategy, function of the architecture and application characteristics. * . While at LRC Itaca, University of Versailles and CEA DAM. 1. Deep jam was first presented in a conference . This longer version describes a compilation algorithm at much greater depth, and draws a pragmatic roadmap to implement deep jam while optimizing the profitability of its steering heuristics. It also reports on the successful optimization of two additional applications, including the SPEC benchmark Gzip.
This paper introduces our work on parallelizing unstructured mesh applications in shared memory. ... more This paper introduces our work on parallelizing unstructured mesh applications in shared memory. Our approach uses task-based runtime and Divide and Conquer recursive bissection strategy for the work decomposition. We demonstrate this parallelization strategy on the unstructured mesh assembly step of an industrial CFD application. Preliminary results show a speedup of 1.8x on a 12 cores node and a performance on Xeon Phi equivalent to 15 Ivy Bridge cores, with a parallel efficiency higher than 90% on the physical cores.
Out-of-order mechanisms in recent microarchitectures do a very good job at hiding latencies and i... more Out-of-order mechanisms in recent microarchitectures do a very good job at hiding latencies and improving performance. However, they come with limitations not easily modeled statically, and hard to quantify exactly even dynamically. This paper will present Uop Flow Simulation (UFS), a loop performance prediction technique accounting for such restrictions by combining static analysis and cycle-driven simulation. UFS simulates the behavior of the execution pipeline when executing a loop. It handles instruction latencies, dependencies, out-of-order resource consumption and other low-level details while completely ignoring semantics. We will use a UFS prototype to validate our approach on Sandy Bridge using loops from real-world HPC applications, showing it is both accurate and very fast (reaching simulation speeds of hundreds of thousands of cycles per second).
This paper presents an empirical approach to measuring and modeling the energy consumption of mul... more This paper presents an empirical approach to measuring and modeling the energy consumption of multicore processors. The modeling approach allows us to find a breakdown of the energy consumption among a set of key hardware components, also called HW nodes. We explicitly model the frontend and the back-end in terms of the number of instructions executed. We also model the L1, L2 and L3 caches. Furthermore, we explicitly model the static and dynamic energy consumed by the the uncore and core components. From a software perspective, our methodology allows us to correlate energy to the executed code, which helps find opportunities for code optimization and tuning. We use binary analysis and hardware counters for performance characterization. Although, we use the on-chip counters (RAPL) for energy measurement, our methodology does not rely on a specific method for energy measurement. Thus, it is portable and easy to deploy in various computing environments. We validate our energy model using two Intel processors with a set of HPC codelets, where data sizes are varied to come from the L1, L2 and L3 caches and show 3% average modeling error. We present a comprehensive analysis and show energy consumption differences between kernels and relate those differences to the algorithms that are implemented. Finally, we discuss how vectorization leads to energy savings compared to non-vectorized codes. CCS Concepts •Computing methodologies → Modeling methodologies; •Hardware → Power and energy; •Computer systems organization → Multicore architectures; * Abdelhafid Mazouz contributed to this work as an Intel employee. He is now at Bull/Atos.
During the last 5 years, thanks to huge progress in IC technology, microprocessor architecture ha... more During the last 5 years, thanks to huge progress in IC technology, microprocessor architecture has made condiderable progress. More recently, the thermal wall (limiting the increase in frequency) has put more focus on microprocessor architecture pushing ahead multicore. In this lecture we will review most of recent progress in microprocessor architecture (out of order execution, superscalar, vector extensions, multi/hyperthreading, multilevel caches, multicore). The emphasis will be set on the impact of these new features on programming and performance tuning.
Zenodo (CERN European Organization for Nuclear Research), Mar 28, 2022
Targeting Real Chemical Accuracy at the Exascale project has received funding from the European U... more Targeting Real Chemical Accuracy at the Exascale project has received funding from the European Union Horizon 2020 research and innovation program under Grant Agreement No. 952165. vi of vii D3.2-Initial public release of high-performance software components List of Figures The internal representation of matrix data. The matrices are stored as blocks of dimension (MC,KC). The blocks are further split into tiles of dimension (MR,NR
The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in... more The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in finding the best "matches" between advanced hardware capabilities and the software used to program applications, so that top performance will be achieved. Several benchmarks show very disappointing performance progress over the last decade, clearly indicating a mismatch between hardware and software. To remedy this problem, it is important that key performance enablers at the software level-autotuning, performance analysis tools, full application optimization-are understood. For each area, we highlight major limitations and most promising approaches to reaching better performance and energy levels. Finally, we conclude by analyzing hardware and software design, trying to pave the way for more tightly integrated hardware and software codesign.
TREXIO is an open-source file format and library developed for the storage and manipulation of da... more TREXIO is an open-source file format and library developed for the storage and manipulation of data produced by quantum chemistry calculations. It is designed with the goal of providing a reliable and efficient method of storing and exchanging wave function parameters and matrix elements, making it an important tool for researchers in the field of quantum chemistry. In this work, we present an overview of the TREXIO file format and library. The library consists of a front-end implemented in the C programming language and two different back-ends: a text back-end and a binary back-end utilizing the HDF5 library which enables fast read and write operations. It is compatible with a variety of platforms and has interfaces for the Fortran, Python, and OCaml programming languages. In addition, a suite of tools has been developed to facilitate the use of the TREXIO format and library, including converters for popular quantum chemistry codes and utilities for validating and manipulating data stored in TREXIO files. The simplicity, versatility, and ease of use of TREXIO make it a valuable resource for researchers working with quantum chemistry data.
HAL (Le Centre pour la Communication Scientifique Directe), 2008
A number of computational applications lack instruction-level parallelism. This loss is particula... more A number of computational applications lack instruction-level parallelism. This loss is particularly acute on sequences of dependent instructions on wide-issue or deeply pipelined architectures. We consider four real applications from computational biology, cryptanalysis, and data compression. These applications are characterized by long sequences of dependent instructions, irregular control-flow and intricate scalar and memory dependence patterns. While these benchmarks exhibit good memory locality and branch-predictability, state-of-the-art compiler optimizations fail to exploit much instruction-level parallelism. This paper shows that major performance gains are possible on such applications, through a loop transformation called deep jam. This transformation reshapes the control-flow of a program to facilitate the extraction of independent computations through classical back-end techniques. Deep jam combines accurate dependence analysis and control speculation, with a generalized form of recursive, multi-variant unroll-and-jam; it brings together independent instructions across irregular control structures, removing memory-based dependences through scalar and array renaming. This optimization contributes to the extraction of fine-grain parallelism in irregular applications. We propose a feedback-directed deep jam algorithm, selecting a jamming strategy, function of the architecture and application characteristics.
HAL (Le Centre pour la Communication Scientifique Directe), 2008
A number of computational applications lack instruction-level parallelism. This loss is particula... more A number of computational applications lack instruction-level parallelism. This loss is particularly acute on sequences of dependent instructions on wide-issue or deeply pipelined architectures. We consider four real applications from computational biology, cryptanalysis, and data compression. These applications are characterized by long sequences of dependent instructions, irregular control-flow and intricate scalar and memory dependence patterns. While these benchmarks exhibit good memory locality and branch-predictability, state-of-the-art compiler optimizations fail to exploit much instruction-level parallelism. This paper shows that major performance gains are possible on such applications, through a loop transformation called deep jam. This transformation reshapes the control-flow of a program to facilitate the extraction of independent computations through classical back-end techniques. Deep jam combines accurate dependence analysis and control speculation, with a generalized form of recursive, multi-variant unroll-and-jam; it brings together independent instructions across irregular control structures, removing memory-based dependences through scalar and array renaming. This optimization contributes to the extraction of fine-grain parallelism in irregular applications. We propose a feedback-directed deep jam algorithm, selecting a jamming strategy, function of the architecture and application characteristics. * . While at LRC Itaca, University of Versailles and CEA DAM. 1. Deep jam was first presented in a conference . This longer version describes a compilation algorithm at much greater depth, and draws a pragmatic roadmap to implement deep jam while optimizing the profitability of its steering heuristics. It also reports on the successful optimization of two additional applications, including the SPEC benchmark Gzip.
This paper introduces our work on parallelizing unstructured mesh applications in shared memory. ... more This paper introduces our work on parallelizing unstructured mesh applications in shared memory. Our approach uses task-based runtime and Divide and Conquer recursive bissection strategy for the work decomposition. We demonstrate this parallelization strategy on the unstructured mesh assembly step of an industrial CFD application. Preliminary results show a speedup of 1.8x on a 12 cores node and a performance on Xeon Phi equivalent to 15 Ivy Bridge cores, with a parallel efficiency higher than 90% on the physical cores.
Out-of-order mechanisms in recent microarchitectures do a very good job at hiding latencies and i... more Out-of-order mechanisms in recent microarchitectures do a very good job at hiding latencies and improving performance. However, they come with limitations not easily modeled statically, and hard to quantify exactly even dynamically. This paper will present Uop Flow Simulation (UFS), a loop performance prediction technique accounting for such restrictions by combining static analysis and cycle-driven simulation. UFS simulates the behavior of the execution pipeline when executing a loop. It handles instruction latencies, dependencies, out-of-order resource consumption and other low-level details while completely ignoring semantics. We will use a UFS prototype to validate our approach on Sandy Bridge using loops from real-world HPC applications, showing it is both accurate and very fast (reaching simulation speeds of hundreds of thousands of cycles per second).
This paper presents an empirical approach to measuring and modeling the energy consumption of mul... more This paper presents an empirical approach to measuring and modeling the energy consumption of multicore processors. The modeling approach allows us to find a breakdown of the energy consumption among a set of key hardware components, also called HW nodes. We explicitly model the frontend and the back-end in terms of the number of instructions executed. We also model the L1, L2 and L3 caches. Furthermore, we explicitly model the static and dynamic energy consumed by the the uncore and core components. From a software perspective, our methodology allows us to correlate energy to the executed code, which helps find opportunities for code optimization and tuning. We use binary analysis and hardware counters for performance characterization. Although, we use the on-chip counters (RAPL) for energy measurement, our methodology does not rely on a specific method for energy measurement. Thus, it is portable and easy to deploy in various computing environments. We validate our energy model using two Intel processors with a set of HPC codelets, where data sizes are varied to come from the L1, L2 and L3 caches and show 3% average modeling error. We present a comprehensive analysis and show energy consumption differences between kernels and relate those differences to the algorithms that are implemented. Finally, we discuss how vectorization leads to energy savings compared to non-vectorized codes. CCS Concepts •Computing methodologies → Modeling methodologies; •Hardware → Power and energy; •Computer systems organization → Multicore architectures; * Abdelhafid Mazouz contributed to this work as an Intel employee. He is now at Bull/Atos.
During the last 5 years, thanks to huge progress in IC technology, microprocessor architecture ha... more During the last 5 years, thanks to huge progress in IC technology, microprocessor architecture has made condiderable progress. More recently, the thermal wall (limiting the increase in frequency) has put more focus on microprocessor architecture pushing ahead multicore. In this lecture we will review most of recent progress in microprocessor architecture (out of order execution, superscalar, vector extensions, multi/hyperthreading, multilevel caches, multicore). The emphasis will be set on the impact of these new features on programming and performance tuning.
Zenodo (CERN European Organization for Nuclear Research), Mar 28, 2022
Targeting Real Chemical Accuracy at the Exascale project has received funding from the European U... more Targeting Real Chemical Accuracy at the Exascale project has received funding from the European Union Horizon 2020 research and innovation program under Grant Agreement No. 952165. vi of vii D3.2-Initial public release of high-performance software components List of Figures The internal representation of matrix data. The matrices are stored as blocks of dimension (MC,KC). The blocks are further split into tiles of dimension (MR,NR
The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in... more The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in finding the best "matches" between advanced hardware capabilities and the software used to program applications, so that top performance will be achieved. Several benchmarks show very disappointing performance progress over the last decade, clearly indicating a mismatch between hardware and software. To remedy this problem, it is important that key performance enablers at the software level-autotuning, performance analysis tools, full application optimization-are understood. For each area, we highlight major limitations and most promising approaches to reaching better performance and energy levels. Finally, we conclude by analyzing hardware and software design, trying to pave the way for more tightly integrated hardware and software codesign.
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Papers by William Jalby