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M. Violante

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Marijke Coetzee

North West University Potchefstroom

Cristina Bicchieri

University of Pennsylvania

Kansas State University

University of Chicago

Ucla

University of Lorraine

Washington Center for Consciousness Studies

Raghu Vamsi Potukuchi

Jaypee Institute of Information Technology

spyros G tzafestas

National Technical University of Athens

Dragos Simandan

Brock University

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Papers by M. Violante

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009

Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and av... more Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic. This paper presents a new way for the analysis of the impact of Single Event Effects in Flash-based FPGAs. We proposed a new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function. The experimental results achieved by fault injection demonstrated the feasibility of the proposed method and show that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.

A source-to-source compiler for generating dependable software

Proceedings First IEEE International Workshop on Source Code Analysis and Manipulation

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

ABSTRACT The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not ... more ABSTRACT The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not yet a reality due to concerns still existing about the device reliability; therefore, more conservative approaches based on anti-fuse FPGAs are currently preferred. The major concern about the use of such devices in space stems from their sensitivity to ionizing radiation, which may alter the content of the design the device implements, and which forces to adopt error mitigation techniques that have very high resource overheads. In this paper we analyze a realistic case study taken from a future space mission, and we show how mitigation techniques that combine hardware and software redundancy can provide very good fault tolerance capabilities to designs that include processor cores, while reducing significantly the overhead of the mitigation technique with respect to the hardware redundancy approach that is nowadays used.

Behavioral-level test vector generation for system-on-chip designs

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

Co-design tools represent an effective solution for reducing costs and shortening time-to-market,... more Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when system-on-chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test sequences, which can be reused during the following design steps, from the system-level specification to the gate-level description. This would significantly increase the chance

Exploiting logic simulation to improve simulation-based sequential ATPG

Proceedings Sixth Asian Test Symposium (ATS'97)

ABSTRACT

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors

Defect and Fault Tolerance in VLSI Systems, 2005

Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the t... more Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting processor memory elements such as state registers inside the processor control unit, or temporary registers inside the arithmetic and logic unit. In this paper we

Speeding-Up Fault Injection Campaigns in VHDL Models

Lecture Notes in Computer Science, 2000

ABSTRACT

Validation of the dependability of can-based networked systems

The validation of networked systems is mandatory to guarantee the dependability levels that inter... more The validation of networked systems is mandatory to guarantee the dependability levels that international standards impose in many safety-critical applications. In this paper we present an environment to study how soft errors affecting the memory elements of network nodes in CAN-based systems may alter the dynamic behavior of a car. The experimental evidence of the effectiveness of the approach is

Self checking circuit optimization by means of fault injection analysis: A case study on reed solomon decoders

Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium, 2007

This paper shows how the use of exhaustive fault injection campaigns in conjunction with the anal... more This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection campaigns on a Reed-Solomon Decoder demonstrated that by observing the occurred errors and the correspondent detection module has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

Optimization of self checking FIR filters by means of fault injection analysis

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007

In this paper the design of a FIR filter with self checking capabilities based on the residue che... more In this paper the design of a FIR filter with self checking capabilities based on the residue checking is analyzed. Usually the set of residues used to check the consistency of the results of the FIR filter are based of theoretic considerations about the dynamic range available with a chosen set of residues, the arithmetic characteristics of the errors caused by a fault and on the characteristic of the filter implementation. This analysis is often difficult to perform and, to obtain an acceptable fault coverage the set of chosen residues is overestimated. obtained result a and therefore requires that Instead, in this paper we show how using an exhaustive fault injection campaigns allows to efficiently select the best set of residues. Experimental results coming from fault injection campaigns on a 16 taps FIR filter demonstrated that by observing the occurred errors and the detection modules corresponding to different residue has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

System safety through automatic high-level code transformations: An experimental evaluation

This paper deals with a software modification strategy allowing the on-line detection of transien... more This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safetycritical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

Instruction and data caches are well known architectural solutions that allow significantly impro... more Instruction and data caches are well known architectural solutions that allow significantly improving the performance of high-end processors. Due to their sensitivity to soft errors they are often disabled in safety critical applications, thus sacrificing performance for improved dependability. In this paper we report an accurate analysis of the effects of soft errors in the instruction and data caches of a soft core implementing the SPARC architecture. Thanks to an efficient simulationbased fault injection environment we developed, we are able to present in this paper an extensive analysis of the effects of soft errors on a processor running several applications under different memory configurations. The procedure we followed allows the precise computation of the processor failure rate when the cache is enabled even without resorting to expensive radiation experiments. * This work has been partially supported by the Center of Excellence on Multimedia Radiocommunications (CERCOM) of Politecnico di Torino.

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices

12th IEEE International On-Line Testing Symposium (IOLTS'06)

Reconfigurable Compute Fabrics (RCFs) are cellular architectures in which an array of computing e... more Reconfigurable Compute Fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety-or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced by transient faults within the resources of an RCF Motorola MRC6011 and we resorted to extensive fault injection to investigate the effects of transient faults

Recovery scheme for hardening system on programmable chips

2009 10th Latin American Test Workshop, 2009

... Massimo Violante, Matteo Sonza Reorda Politecnico di Torino, Italy {massimo.violante,matteo.s... more

Methodologies to Study Frequency-Dependent Single Event Effects Sensitivity in Flash-Based FPGAs

IEEE Transactions on Nuclear Science, 2009

Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

IEEE Transactions on Nuclear Science, 2005

Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Si... more Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

Simulation-based analysis of SEU effects in SRAM-based FPGAs

IEEE Transactions on Nuclear Science, 2004

Long Duration Balloon flights for the evaluation of radiation effects on electronic systems

In this paper the proposal for a long duration polar flight program to study the radiation effect... more

1. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories

A programmable BIST approach for the diagnosis of embedded memory cores

ABSTRACT This paper addresses the issue of testing and diagnosing a memory core embedded in a com... more ABSTRACT This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows the programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost for test program development, maximizing the flexibility (e.g., minimizing the cost of reusing the solution when a different memory type has to be supported), minimizing the cost for the external ATE.

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009

Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and av... more Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic. This paper presents a new way for the analysis of the impact of Single Event Effects in Flash-based FPGAs. We proposed a new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function. The experimental results achieved by fault injection demonstrated the feasibility of the proposed method and show that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.

A source-to-source compiler for generating dependable software

Proceedings First IEEE International Workshop on Source Code Analysis and Manipulation

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

ABSTRACT The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not ... more ABSTRACT The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not yet a reality due to concerns still existing about the device reliability; therefore, more conservative approaches based on anti-fuse FPGAs are currently preferred. The major concern about the use of such devices in space stems from their sensitivity to ionizing radiation, which may alter the content of the design the device implements, and which forces to adopt error mitigation techniques that have very high resource overheads. In this paper we analyze a realistic case study taken from a future space mission, and we show how mitigation techniques that combine hardware and software redundancy can provide very good fault tolerance capabilities to designs that include processor cores, while reducing significantly the overhead of the mitigation technique with respect to the hardware redundancy approach that is nowadays used.

Behavioral-level test vector generation for system-on-chip designs

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

Co-design tools represent an effective solution for reducing costs and shortening time-to-market,... more Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when system-on-chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test sequences, which can be reused during the following design steps, from the system-level specification to the gate-level description. This would significantly increase the chance

Exploiting logic simulation to improve simulation-based sequential ATPG

Proceedings Sixth Asian Test Symposium (ATS'97)

ABSTRACT

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors

Defect and Fault Tolerance in VLSI Systems, 2005

Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the t... more Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting processor memory elements such as state registers inside the processor control unit, or temporary registers inside the arithmetic and logic unit. In this paper we

Speeding-Up Fault Injection Campaigns in VHDL Models

Lecture Notes in Computer Science, 2000

ABSTRACT

Validation of the dependability of can-based networked systems

The validation of networked systems is mandatory to guarantee the dependability levels that inter... more The validation of networked systems is mandatory to guarantee the dependability levels that international standards impose in many safety-critical applications. In this paper we present an environment to study how soft errors affecting the memory elements of network nodes in CAN-based systems may alter the dynamic behavior of a car. The experimental evidence of the effectiveness of the approach is

Self checking circuit optimization by means of fault injection analysis: A case study on reed solomon decoders

Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium, 2007

This paper shows how the use of exhaustive fault injection campaigns in conjunction with the anal... more This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection campaigns on a Reed-Solomon Decoder demonstrated that by observing the occurred errors and the correspondent detection module has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

Optimization of self checking FIR filters by means of fault injection analysis

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007

In this paper the design of a FIR filter with self checking capabilities based on the residue che... more In this paper the design of a FIR filter with self checking capabilities based on the residue checking is analyzed. Usually the set of residues used to check the consistency of the results of the FIR filter are based of theoretic considerations about the dynamic range available with a chosen set of residues, the arithmetic characteristics of the errors caused by a fault and on the characteristic of the filter implementation. This analysis is often difficult to perform and, to obtain an acceptable fault coverage the set of chosen residues is overestimated. obtained result a and therefore requires that Instead, in this paper we show how using an exhaustive fault injection campaigns allows to efficiently select the best set of residues. Experimental results coming from fault injection campaigns on a 16 taps FIR filter demonstrated that by observing the occurred errors and the detection modules corresponding to different residue has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

System safety through automatic high-level code transformations: An experimental evaluation

This paper deals with a software modification strategy allowing the on-line detection of transien... more This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safetycritical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

Instruction and data caches are well known architectural solutions that allow significantly impro... more Instruction and data caches are well known architectural solutions that allow significantly improving the performance of high-end processors. Due to their sensitivity to soft errors they are often disabled in safety critical applications, thus sacrificing performance for improved dependability. In this paper we report an accurate analysis of the effects of soft errors in the instruction and data caches of a soft core implementing the SPARC architecture. Thanks to an efficient simulationbased fault injection environment we developed, we are able to present in this paper an extensive analysis of the effects of soft errors on a processor running several applications under different memory configurations. The procedure we followed allows the precise computation of the processor failure rate when the cache is enabled even without resorting to expensive radiation experiments. * This work has been partially supported by the Center of Excellence on Multimedia Radiocommunications (CERCOM) of Politecnico di Torino.

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices

12th IEEE International On-Line Testing Symposium (IOLTS'06)

Reconfigurable Compute Fabrics (RCFs) are cellular architectures in which an array of computing e... more Reconfigurable Compute Fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety-or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced by transient faults within the resources of an RCF Motorola MRC6011 and we resorted to extensive fault injection to investigate the effects of transient faults

Recovery scheme for hardening system on programmable chips

2009 10th Latin American Test Workshop, 2009

... Massimo Violante, Matteo Sonza Reorda Politecnico di Torino, Italy {massimo.violante,matteo.s... more

Methodologies to Study Frequency-Dependent Single Event Effects Sensitivity in Flash-Based FPGAs

IEEE Transactions on Nuclear Science, 2009

Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

IEEE Transactions on Nuclear Science, 2005

Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Si... more Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

Simulation-based analysis of SEU effects in SRAM-based FPGAs

IEEE Transactions on Nuclear Science, 2004

Long Duration Balloon flights for the evaluation of radiation effects on electronic systems

In this paper the proposal for a long duration polar flight program to study the radiation effect... more

1. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories

A programmable BIST approach for the diagnosis of embedded memory cores

ABSTRACT This paper addresses the issue of testing and diagnosing a memory core embedded in a com... more ABSTRACT This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows the programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost for test program development, maximizing the flexibility (e.g., minimizing the cost of reusing the solution when a different memory type has to be supported), minimizing the cost for the external ATE.