Ulkuhan Guler

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Jayjit Majumdar

University of Kalyani

Anis Nurashikin Nordin

International Islamic University Malaysia

Sudheesh K Shukla, PhD

LOVELY PROFESSIONAL UNIVERSITY

Muharrem Keskin

Mustafa Kemal University

Lehigh University

Howard University

Bogazici University

Bogazici University

Middle East Technical University

Robert B Staszewski

University College of Dublin

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Papers by Ulkuhan Guler

Recent Topics on Programmable Logic Array

The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Afte... more The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. After recent improvement techniques on PLA, PLA becomes more attractive for designers especially in GHz technology with deep sub-micron sizing. In this paper we will try to introduce the cross-talk problem solution in DSM, in PLA Network and also try to give the usage of PLA in GHz technology and the advantage of PLA as a solution of Timing Closure.

Constraint driven dual-rail PLA module generator with embedded 2-input logic cells

This paper describes design and development of a module generator which is based on a timing-driv... more This paper describes design and development of a module generator which is based on a timing-driven design methodology. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. Almost all of these logic cells have two inputs. 2-input logic cells are embedded in place of conventional AND/OR planes. By using the 2-input logic cells, some classes of logic functions can be implemented in a smaller circuit area. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters.

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A high speed IC Random Number Generator based on phase noise in ring oscillators

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

Page 1. A High Speed IC Random Number Generator Based on Phase Noise in Ring Oscillators ¨Ulkühan... more

Modeling phase noise and jitter in subthreshold region and assessing the randomness performance of CMOS ring oscillators

by Ulkuhan Guler and Günhan Dündar

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012

ABSTRACT This paper analyzes the phase noise and jitter issues for random number generation in th... more ABSTRACT This paper analyzes the phase noise and jitter issues for random number generation in the weak inversion operating region of CMOS Ring Oscillators (RO) with the purpose of increasing the randomness of a RO. To the best of our knowledge, this is the first study on modeling phase noise and jitter in subthreshold region and assessing the randomness performance in this region. Phase noise and jitter equations are derived. Furthermore, randomness equations are obtained from these equations and compared with the strong inversion counterparts to show the increase in randomness. Inverter-based Ring Oscillators (IbRO) and Differential Ring Oscillators (DROs) are examined. For design and analysis, 0.25μm standard CMOS process has been used with a supply voltage of 0.5V. Decreasing the supply voltage of IbRO from 2.5V to 0.5V results in 68.7 times increase in randomness and 1297 times reduction in energy. In DRO case, the same reduction in supply voltage results in 7.64 times increase in randomness and 51 times reduction in energy.

Monolithic implementation of a double-scroll chaotic attractor and application to random number generation

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

This paper presents an IC realization of a simple autonomous continuous-time chaotic oscillator, ... more This paper presents an IC realization of a simple autonomous continuous-time chaotic oscillator, which realizes the double-scroll-like chaotic equation. Prototype ICs verifying the feasibility and the correct operation of the chaotic oscillator have been designed and fabricated by using HHNECs 0.25μm eFlash process with a supply voltage of 2.5V. Experimental results from a tested IC are given. Implemented circuit occupies

IC truly random number generators based on regular & chaotic sampling of chaotic waveforms

Nonlinear Theory and Its Applications, IEICE, 2011

抄録 Two random number generation methods based on regular and chaotic sampling of chaotic waveform... more

5G-3 A Low-Noise Front-End Circuit for 2D cMUT Arrays

Ultrasonics, IEEE Symposium, 2006

cMUT technology enables 2D array design with front-end electronic integration through flip-chip b... more cMUT technology enables 2D array design with front-end electronic integration through flip-chip bonding or cMUT-on-CMOS process. The size of a 2D array element is constrained in both dimensions due to the aperture sampling criteria, and therefore should be less than or equal to the half of the wavelength in both dimensions. Considering large parasitic capacitances introduced by the interconnections, such

A digital IC Random Number Generator with logic gates only

by Ulkuhan Guler and Günhan Dündar

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

... 7, pp. 1395-1404, Jul. 2004. [9] S. Ergun and S. Ozoguz, "Truly random number generators... more ... 7, pp. 1395-1404, Jul. 2004. [9] S. Ergun and S. Ozoguz, "Truly random number generators based on non-autonomous continuous-time chaos," Int. J. Circ. Theor. ... [19] U. GuIer and S. Ergun, "A high speed, fully digital ic random number generator," in Proc. ISCAS'lO, 2010. 242

Maximizing randomness in ring oscillators for security applications

by Ulkuhan Guler and Günhan Dündar

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011

Existing works on generating random bits by ring oscillators (ROs) mostly do not have detailed an... more Existing works on generating random bits by ring oscillators (ROs) mostly do not have detailed analysis on phase noise and jitter which are the entropy source of a random number generator. This paper analyzes the suitability of existing ROs for random number generation and possible improvements in order to increase the randomness of a RO. Randomness equations are derived, to

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells

IEICE Transactions on Information and Systems, 2005

This paper describes the design and development of a module generator for a dual-rail PLA with em... more This paper describes the design and development of a module generator for a dual-rail PLA with embedded 2-input logic cells for 0.35 µm CMOS technology. In order to automatically generate logic-cell based PLA layouts from circuit specifications, a module generator as a design automation tool of logic-cell based PLA is developed with a structural improvement. This module generator is based on a timing-driven design methodology and consists of logic synthesis, transistor sizing and logic cell generation, stimulus generation, HDL model generation parts. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. The layout is generated by using 0.35 µm, 3-metal-layer CMOS technology. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters. The design complexity which is becoming an important issue for VLSI circuits can be reduced partially and human caused errors are minimized by module generator. A PLA layout in GDS-II form and an HDL model behavior of a Boolean function which has 64-bit input, 1bit output and 220 product term can be generated within 8 minutes on a SunUltraSPARC-III 900 MHz processor. A very short time is required to compile the module, and this makes it feasible for designers to try many different design configurations in order to get the better one. key words: PLA, module generator, cell generation, HDL behavior generation received the B.S., M.S., and Ph.D. degrees in electronics engineering from

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A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2011

Summary: A novel random number generation method based on chaotic sampling of regular waveform is... more

Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source

by Ulkuhan Guler and Günhan Dündar

IEEE Transactions on Circuits and Systems I: Regular Papers, 2000

ABSTRACT In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Gene... more ABSTRACT In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 $mu$m standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case.

A high speed, fully digital IC random number generator

AEU - International Journal of Electronics and Communications, 2012

System-on-a-chip solutions require hardware based integrated circuit random number generators for... more System-on-a-chip solutions require hardware based integrated circuit random number generators for trustworthy transmission of information. This paper presents, a fully digital, high speed ASIC random number generator based on ring oscillators. Prototypes have been designed and fabricated in HHNEC's 0.25 m eFlash process with a supply voltage of 2.5 V. The circuit occupies 0.052 mm 2 and dissipates 0.095 W of power. IC design level experiences, measurements, analysis of measurements and statistical test results are also demonstrated. Instead of resilient function, employed in the previous ring oscillators based design, which decreases the throughput by a factor of 16, we propose to use only a simple Von Neumann corrector which improves this result by a factor of 4. We achieved fulfilled test results from NIST 800-22 test suit after Von Neumann corrector with a sampling frequency of 74 MHz. Since, Von Neumann corrector is used as a post-processor, the throughput becomes 18.5 Mbps. Furthermore, we propose to use doubled ring oscillators structure, thus, a 125 Mbps throughput, which is the highest data rate to date with fulfilled test results, is attained without any postprocessing. The results were repeatable numerous times.

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Investigating flicker noise effect on randomness of CMOS ring oscillator based true random number generators

by Günhan Dündar and Ulkuhan Guler

2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014

Recent Topics on Programmable Logic Array

Constraint driven dual-rail PLA module generator with embedded 2-input logic cells

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A high speed IC Random Number Generator based on phase noise in ring oscillators

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

Page 1. A High Speed IC Random Number Generator Based on Phase Noise in Ring Oscillators ¨Ulkühan... more

Modeling phase noise and jitter in subthreshold region and assessing the randomness performance of CMOS ring oscillators

by Ulkuhan Guler and Günhan Dündar

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012

Monolithic implementation of a double-scroll chaotic attractor and application to random number generation

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

IC truly random number generators based on regular & chaotic sampling of chaotic waveforms

Nonlinear Theory and Its Applications, IEICE, 2011

抄録 Two random number generation methods based on regular and chaotic sampling of chaotic waveform... more

5G-3 A Low-Noise Front-End Circuit for 2D cMUT Arrays

Ultrasonics, IEEE Symposium, 2006

A digital IC Random Number Generator with logic gates only

by Ulkuhan Guler and Günhan Dündar

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

Maximizing randomness in ring oscillators for security applications

by Ulkuhan Guler and Günhan Dündar

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells

IEICE Transactions on Information and Systems, 2005

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A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2011

Summary: A novel random number generation method based on chaotic sampling of regular waveform is... more

Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source

by Ulkuhan Guler and Günhan Dündar

IEEE Transactions on Circuits and Systems I: Regular Papers, 2000

A high speed, fully digital IC random number generator

AEU - International Journal of Electronics and Communications, 2012

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Investigating flicker noise effect on randomness of CMOS ring oscillator based true random number generators

by Günhan Dündar and Ulkuhan Guler

2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014

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