Papers by Sheng-Lung Wang
Delay modeling for buffered RLY/RLC trees
ABSTRACT For deep-submicron, high-performance circuits, the inductive effect plays a very importa... more ABSTRACT For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, the authors derived accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. The formulae could handle balanced and unbalanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, with an average error of within 5.51% based on the 180 nm technology. The simulations show that the formulae are more accurate than previous works.
International Conference on Computer Aided Design, Nov 5, 2007
As nanometer technology advances, the post-CMP dielectric thickness variation control becomes cru... more As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and lead to explosion of mask data. It is thus desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive postlayout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies a novel two-pass, top-down planarity-driven routing framework, which employs a new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve more balanced wire distribution than state-of-the-art works.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb 1, 2009
As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variati... more As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following timeconsuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.
2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
As nanometer technology advances, the post-CMP dielectric thickness variation control becomes cru... more As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and lead to explosion of mask data. It is thus desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive postlayout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies a novel two-pass, top-down planarity-driven routing framework, which employs a new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve more balanced wire distribution than state-of-the-art works.
Delay modeling for buffered RLY/RLC trees
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
ABSTRACT For deep-submicron, high-performance circuits, the inductive effect plays a very importa... more ABSTRACT For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, the authors derived accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. The formulae could handle balanced and unbalanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, with an average error of within 5.51% based on the 180 nm technology. The simulations show that the formulae are more accurate than previous works.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009
As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variati... more As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following timeconsuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.
For deep-submicron, high-performance circuits, the inductive effect plays a very important role i... more For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, we derive accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. Our formulae can handle balanced and unbalanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, with an average error of within 5.51% based on the 180 nm technology. The simulations show that our formulae are more accurate than previous works.
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Papers by Sheng-Lung Wang