Sergei Kostin

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Aroutis Foster

Drexel University

Robert Dahlberg

Virginia Commonwealth University

J. Michael Spector

University of North Texas

Avik Mitra

Indian Statistical Institute, Calcutta

George Veletsianos

University of Minnesota - Twin Cities

David Wardell

Abhishek Ray

KIIT University

Fabio Zanasi

University College London

Jana August

Zentrum für Literatur- und Kulturforschung, Berlin

Mauro Berumen

Universidad del Caribe

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Papers by Sergei Kostin

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

The conventional design techniques struggle with integration density and constantly strengthening... more The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification, path delay fault simulation, circuit reliability analysis e.g. Bias Temperature Instability (BTI) induced aging, and in several others. In this paper, we propose a scalable simulation based hierarchical technique for explicit identification of true timing-critical paths in sequential circuits. We explore the circuits at two levels - at the flat gate-level and at a higher level as a network of modules or sub-circuits. The result of timing analysis carried out at the gate-level is used for calculating the delays on the topological critical paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)

In this paper we present a very fast fault simulation method for sequential circuits, which is ba... more In this paper we present a very fast fault simulation method for sequential circuits, which is based on accommodation of exact parallel critical path tracing in combinational circuits for using it also in case of sequential circuits. Formulas are developed for parallel on-line analysis of the faults to classify them into two classes, which are eligible for combinational simulation, and which are not. The latter class of faults has to be simulated by any conventional fault simulation method used for sequential circuits. Combining two approaches to fault simulation - the combinational and sequential ones - allows dramatic speed-up of fault simulation in sequential circuits, which is demonstrated by experimental results.

A scalable technique to identify true critical paths in sequential circuits

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.

Digitaalskeemide funktsionaalse isetestimise kvaliteedi parandamine. Improvement of the Functional Selftest Quality for Digital Circuits

Fast identification of true critical paths in sequential circuits

The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small s...

Experimental comparison of different diagnosis algorithms in the BIST environment

The 16th Iasted International Conference on Applied Simulation and Modelling, Aug 9, 2007

ABSTRACT In this paper a study about fault diagnosing procedures in a Built-in Self-Test environm... more ABSTRACT In this paper a study about fault diagnosing procedures in a Built-in Self-Test environment is presented. A new algorithm is proposed based on bisection strategy. Instead of bisection of patterns in test sequences as a known approach, in the proposed bisection procedure the diagnostic information inherent in test patterns is taken into account. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are necessarily needed to be fixed for diagnosis. This feature allows tradeoff between time cost and diagnostic resolution. A possibility is shown to improve the diagnostic resolution by using multiple signature analyzers. The proposed method is compared with three known fault diagnosis methods: classical Binary Search, Doubling and Jumping. Experimental results demonstrated the feasibility and efficiency of the approach.

Gate-level modelling of NBTI-induced delays under process variations

2016 17th Latin-American Test Symposium (LATS), 2016

Continuous technology scaling poses reliability concerns that directly affect the Integrated Circ... more Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speed-up in simulation.

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Journal of Electronic Testing, 2016

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main relia... more The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.

Comparison of two approaches to improve functional BIST fault coverage

2014 14th Biennial Baltic Electronic Conference (BEC), 2014

Two approaches to improve the fault coverage of functional logic BIST in digital circuits are pro... more Two approaches to improve the fault coverage of functional logic BIST in digital circuits are proposed and investigated. The first approach is based on introducing of additional test points. An experimental tool set is developed for fast evaluation of the number of control points that is needed to achieve 100% fault coverage for the given functional test sequence. A novel algorithm is proposed to minimize the number of control points. The second approach is based on complementing the functional test with additional deterministic test patterns. The pros and cons of both approaches are highlighted and discussed.

Fault Diagnosis in the BIST Environment Based on Bisection of Detected Faults

An optimized fault diagnosing procedure in Built-in Self-Test environment is proposed. Instead of... more An optimized fault diagnosing procedure in Built-in Self-Test environment is proposed. Instead of bisection of patterns in pseudorandom test sequences, in the proposed bisection procedure the diagnostic information inherent in test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. The proposed method is compared with three known fault diagnosis methods: classical Binary Search, Doubling and Jumping. Experimental results have demonstrated the advantages of the proposed method compared to the known methods.

Defect-oriented module-level fault diagnosis in digital circuits

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011

ABSTRACT We propose a hierarchical approach for physical defect diagnosis in combinational or ful... more ABSTRACT We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high diagnostic resolution of the proposed approach.

Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networks

2009 1st Asia Symposium on Quality Electronic Design, 2009

The main objective of this work is to combine the concept of fault model free diagnosis simultane... more The main objective of this work is to combine the concept of fault model free diagnosis simultaneously with causeeffect and effect-cause analysis in digital networks. We consider the diagnosis as a two step task: first, to locate a subset of faulty blocks in a network by using block level fault dictionaries, second, to locate the faulty block in this subset by effect-cause analysis. The size of the fault dictionary depends linearly on the number of blocks to be determined as faulty or not faulty. We propose a measure for evaluating the block-level diagnostic resolution of a given network, and show how this measure can be used for guiding effect-cause diagnostic analysis. Experimental results provide the data which characterize the proposed measure.

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Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009

ABSTRACT The concept of fault model free diagnosis is combined with cause-effect analysis in digi... more ABSTRACT The concept of fault model free diagnosis is combined with cause-effect analysis in digital systems represented as networks of functional blocks. We consider the diagnosis as a task to locate a faulty block in the network by using concise block level topological fault dictionaries. The dictionary does not need fault simulation and represents only the connectivity of blocks to observable checkpoints. We define the distance between the entries (codewords) in the dictionary, and make use of these distances to match the observed test responses to the entries of the dictionary. A measure is proposed for evaluating the block-level diagnosability of a given network which can be used for improving the diagnostic resolution. Experimental results provide the data which characterize the proposed measure and show the efficiency of using topological fault dictionaries.

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems

2009 IEEE International Conference on Microelectronic Systems Education, 2009

In this work, we propose a multifunctional remote e-learning environment for teaching research by... more In this work, we propose a multifunctional remote e-learning environment for teaching research by learning and investigating the problems of fault diagnosis in electronic systems. It is a collection of software tools which allow to simulate a system under diagnosis, emulate a pool of different methods and algorithms of fault location, analyze the efficiency of different embedded self-diagnosing architectures, and investigate the effect of real physical defects in electronic circuits. Hands-on experiments target research teaching issues. The interactive character of the environment makes the experiments attractive and helps to raise the students' curiosity for finding innovative procedures for debugging digital systems.

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SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Accurate prediction of circuit aging is essential to reliable design, in particular for critical ... more Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced V THp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

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Calculation of the diagnosibility of digital circuits without using fault models

2008 11th International Biennial Baltic Electronics Conference, 2008

The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) fac... more The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. The main concern is related to the weak diagnostic capability of BIST. A BIST architecture is described which is based on multiple signature analyzers (SA) to provide better diagnostic resolution. A new conception for the diagnosis of digital circuits, which does not use fault models, and a method for calculating the diagnosibility of the given circuit are presented The results of calculation can be used for redesign of the circuit for better diagnosibility. Experimental results provide the data which characterize the diagnosibility for a family of ISCAS benchmark circuits.

Investigations of the diagnosibility of digital networks with BIST

2009 10th Latin American Test Workshop, 2009

ABSTRACT The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (... more ABSTRACT The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. A conception for diagnosis of digital circuits, which does not use fault models, and methods for calculating the diagnosibility of the given circuit are presented. The proposed measures of diagnosibility can be used for redesign of the circuit to improve the exactness of locating the faults or faulty regions in digital circuits. Experimental results provide the data which characterize the diagnosibility of circuits for the ISCAS benchmark family.

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

2015 16th Latin-American Test Symposium (LATS), 2015

One of the main reliability concerns in the nanoscale logic is the time-dependent variation cause... more One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTIcritical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design.

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Teaching research in the laboratory using diagnosis environment for digital systems

2009 EAEEIE Annual Conference, 2009

ABSTRACT In this work, we propose a multifunctional e-learning environment with remote access for... more ABSTRACT In this work, we propose a multifunctional e-learning environment with remote access for learning, getting hands-on experience, and carrying out laboratory research in developing optimized procedures for locating faults in complex electronic systems. It is a combination of a collection of software tools which simulate a system under diagnosis, emulate a pool of different strategies, methods, and algorithms of diagnostic reasoning and fault location, and allow to experiment with different embedded self-diagnosing architectures. Hands-on experiments target research teaching issues. The interactive character of the environment makes experiments attractive and helps to raise the students&#39; curiosity.

How to Prove that a Circuit is Fault-Free?

2012 15th Euromicro Conference on Digital System Design, 2012

ABSTRACT A new method of test generation based on the concept of partial test groups to prove the... more ABSTRACT A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected part of the circuit. In case of passing of all the test groups, the circuit is proven fault-free. In case when not all test groups will pass, fault diagnosis by a sequential process of extending the fault-free core is possible.