Papers by Sebastian Kaltenstadler
Multi-Processor System-on-Chip FPGAs can utilize programmable logic for compute intensive functio... more Multi-Processor System-on-Chip FPGAs can utilize programmable logic for compute intensive functions, using socalled Accelerators, implementing a heterogeneous computing architecture. Thereby, Embedded Systems can benefit from the computing power of programmable logic while still maintaining the software flexibility of a CPU. As a design option to the well-established RTL design process, Accelerators can be designed using High-Level Synthesis. The abstraction level for the functionality description can be raised to algorithm level by a tool generating HDL code from a high-level language like C/C++. The Xilinx tool Vivado HLS allows the user to guide the generated RTL implementation by inserting compiler pragmas into the C/C++ source code. This paper analyzes the possibilities to improve the performance of an FPGA accelerator generated with Vivado HLS and integrated into a Vivado block design. It investigates, how much the pragmas affect the performance and resource cost and shows pro...
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Papers by Sebastian Kaltenstadler