Mobile phones and smartphones have evolved to be very powerful devices that have the potential to... more Mobile phones and smartphones have evolved to be very powerful devices that have the potential to be utilized in many application areas apart from generic communication. With each passing year, we see increasingly powerful smartphones being manufactured, which have a plethora of powerful embedded sensors like microphone, camera, digital compass, GPS, accelerometer, temperature sensors and many more. Moreover, the ability to easily program today's smartphones, enables us to exploit these sensors, in a wide variety of application such as personal safety, emergency and calamity response, situation awareness, remote activity monitoring, transportation and environment monitoring. In this paper, we survey the existing mobile phone sensing methodologies and application areas. We also formulate the architectural framework of our project, SenseDroid, its utility, limitations and possible future applications.
Professor Nikil Dutt, Chair Embedded systems are increasingly seeing the need for self-awareness ... more Professor Nikil Dutt, Chair Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they execute, and in the manufactured hardware. The notion of selfawareness enables a system to monitor its own state and behavior such that it is capable of making judicious decisions and adapt intelligently. However, emerging Multiprocessor Systems-on-chip (MPSoCs), used by these embedded systems and devices, still treat the elements of intelligence, specifically self-awareness, as a second-class design requirement, supporting them with ad hoc and poorly-developed awareness mechanisms, architectural supports, and system software. This dissertation overcomes these limitations by providing the foundation for a new class of self-aware adaptive MPSoCs called a Cyber-Physical-System-on-Chip (CPSoC). Unlike traditional MPSoCs, CPSoCs are distinguished by an intelligent co-design of the control, communication, and computing (C3) infrastructure while considering both the cyber and physical aspects together so as to adaptively achieve desired objectives and goals. CPSoC's sensor-actuator rich scalable architecture intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness in a principled way. The thesis corroborates, through experiments and FPGA prototypes, the key idea that giving the SoC the freedom to opportunistically adapt the software and the hardware stack by infusing self-awareness mechanisms and steerable knobs across the stack can open up new and otherwise untapped opportunities in energy efficiency, performance, and thermal resilience. xxiv
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
The increased demands of high performance, higher power/energy efficiency, and expanding function... more The increased demands of high performance, higher power/energy efficiency, and expanding functionality are moving traditional MultiProcessor Systems-on-Chips (MPSoCs) towards heterogenous many-core architectures with hundreds to thousands of cores that need to deal with a diverse and rapid stream of dynamically changing applications with competing and conflicting demands and goals. Furthermore, MPSoCs face dramatic manufacturing process variability (as semiconductor technology dives deeper into the nanometer era), and increased vulnerability to environmental and aging effects that induce errors and subsequent faults and failures. In addition, MPSoCs face vexing thermal and heating hazards, creating drastic and harsh environments (e.g., hotspots), that further aggravate aging and wearout phenomena (e.g., NBTI, HCI, TDDB, Electromigration etc. [1]) resulting in increased susceptibility to errors with the immediate consequence of diminishing yield, reliability and reduced usage lifetime [1], [2]. These new demands on MPSoC platforms with increased heterogeneity in interconnected cores result in challenging coupled/coordinated interactions, and hard to fine-tune scores of runtime parameters for sustained efficiency. Consequently, there is a critical need for improved abstraction to manage the complexity, synergistic crosslayer cooperation and adaptations to effectively manage the onchip resources, and new means of actuations and actions to meet the aggressive and competing demands/goals. Additionally, MPSoCs need to sense many more physical phenomena and system states across multiple abstraction levels in order to exploit workload and process variabilities [1], find root causes of faults and failures, as well as identify vulnerabilities (e.g. thermal hotspots, malicious attacks) to take proactive actions. To address these challenges, we present CyberPhysical-Systemson-Chip (CPSoC) [3], a new class of sensor-actuator rich many-core computing platforms that intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness (Figure 1). Unlike traditional MPSoC designs, the CPSoC paradigm co-designs the control, communication, and computing (C3) system that interacts with the physical environment in real-time to modify the system's behavior [4] so as to adaptively achieve desired objectives and Quality-of-Service (QoS). The CPSoC design paradigm enables selfawareness [5] (i.e., the ability of the system to observe its own
The task of architectural Design Space Exploration (DSE) is extremely complex, with multiple arch... more The task of architectural Design Space Exploration (DSE) is extremely complex, with multiple architectural parameters to be tuned and optimized, resulting in a huge design space that needs to be explored efficiently. Furthermore, each architectural parameter and/or design point is critically affected by decisions made at lower levels of abstraction (e.g., layout, choice of transistors, etc.). Ideally designers would like to perform DSE incorporating information and decisions made across multiple layers of design abstraction so that the ensuing design space is both feasible and has good fidelity. Simulation-based methods alone can not deal with this incredibly large and complex design space. To address these issues, this chapter presents an approach for cross-layer architectural DSE that efficiently prunes the large design space and furthermore uses predictive models to avoid expensive simulations. The chapter uses a singlechip heterogeneous single-ISA multiprocessor as an exemplar to demonstrate how the large search space can be covered and evaluated efficiently. A crosslayer approach is presented to cope with the complexity by restricting the search/design space through the use of cross-layer prediction models to avoid too costly full system simulations, coupled with systematic pruning of the design space to enable good coverage of the design space in an efficient manner.
Author(s): Sarma, Santanu | Advisor(s): Dutt, Nikil | Abstract: This thesis presents an efficient... more Author(s): Sarma, Santanu | Advisor(s): Dutt, Nikil | Abstract: This thesis presents an efficient and scalable sense-making framework using machine learning techniques for Internet-of-Things (IoTs) in order to understand users, contexts, and their environments to make meaningful decisions. The proposed sense-making IoT framework, called Essence, employs combination of participatory mobile crowdsensing along with infrastructure sensing to perform sense-making using machine learning techniques. While collaborative mobile crowdsensing enables information to be gathered and shared by users who are directly involved (participatory sensing) or integrated seamlessly as needed (opportunistic sensing) through user mobile platforms, the infrastructure sensing fabric of the Essence framework provides sense-making support for scenarios where mobile sensing platforms are inadequate. To address the scalability needs of the Essence framework, we employ dimensionality reduction techniques such as p...
Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiproc... more Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiprocessor due to their improved power, performance, and energy efficiency for a given chip/die area. However, to fully tap their potential, a systematic exploration of their diverse and vast design space is necessary. In this paper, we present a cross-layer (across application, operating system, and hardware architecture layer) design space exploration (DSE) of single-ISA (Instruction Set Architecture) heterogeneous multicore processors. We deploy predictive models to investigate the interactions and influence of heterogeneity (configurations, number and types of cores), multiobjective allocation strategies, along with diverse types of workloads under system level constraints (such as equal area or power budget). We perform a cross-layer DSE study of heterogeneous multicore processors with four simulated annealing (SA) based task allocation strategies that are more generic and efficient in c...
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
To meet the performance and energy efficiency demands of emerging complex and variable workloads,... more To meet the performance and energy efficiency demands of emerging complex and variable workloads, heterogeneous manycore architectures are increasingly being deployed, necessitating operating systems support for adaptive task allocation to efficiently exploit this heterogeneity in the face of unpredictable workloads. We present SPARTA, a throughput-aware runtime task allocation approach for Heterogeneous manycore Platforms (HMPs) to achieve energy efficiency. SPARTA collects sensor data to characterize tasks at runtime and uses this information to prioritize tasks when performing allocation in order to maximize energy-efficiency (instructions-per-Joule) without sacrificing performance. Our experimental results on heterogeneous manycore architectures executing mixes of MiBench and PARSEC benchmarks demonstrate energy reductions of up to 23% when compared to state-of-the-art alternatives. SPARTA is also scalable with low overhead, enabling energy savings in large-scale architectures with up to hundreds of cores.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
Cyber-physical systems (CPSs) are physical and engineered systems whose operations are monitored,... more Cyber-physical systems (CPSs) are physical and engineered systems whose operations are monitored, coordinated, controlled, and integrated by a computing, control, and communication core. We propose Cyberphysical-System-on-Chip (CPSoC), a new class of sensor and actuator-rich multiprocessor systemson-chip (MPSoCs), that augment MPSoCs with additional onchip and cross-layer sensing and actuation capabilities to enable self-awareness within the observe-decide-act (ODA) paradigm. Unlike traditional MPSoC designs, CPSoC differs primarily on the co-design of computing-communication-control (C3) systems that interacts with the physical environment in real-time in order to adapt system behavior so as to dynamically react to environmental changes while achieving overall design goals. We illustrate CPSoC's potential through a virtual sensor network that accurately estimates run-time power for variability affected subsystems using noisy thermal sensors in improving system goals and Quality-of-Service (QoS).
Australian Journal of Electrical and Electronics Engineering, 2008
Abstract Three adaptive frequency and phase-locked loops (referred as APLL, APLL1, and APLL2) are... more Abstract Three adaptive frequency and phase-locked loops (referred as APLL, APLL1, and APLL2) are presented that uses a modified phase detector for improved performance. These adaptive phase-locked loops (PLL) have considerably superior performance compared to the conventional and Costas PLL in terms of convergence speed, tracking quality, and frequency acquisition range as well as acquisition time under dynamic conditions. The stability and convergence properties of these three adaptive PLLs are studied using Lyapunov methods. Further, the influence of the design parameters on the tracking and noise performance of these PLLs are shown. Unlike conventional PLL, these adaptive PLL have lesser phase and frequency variance and provides smooth estimates of the frequency, phase, and magnitude of the input sinusoid signal. They are also computationally less expensive than the conventional and Costas PLL as there is no need for an additional low pass filter after the multiplier phase detector. Extensive computer simulations are performed to compare and demonstrate their effectiveness for different conditions. Simulation results show that all the three adaptive PLLs outperform conventional and Costas PLL in terms of frequency estimate accuracy and frequency acquisition range. In addition, it is observed from the simulation results that APPL2 has better performance compared the other PLLs in terms of tracking speed, accuracy, and frequency range.
2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2015
In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for... more In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for dynamic workloads executing on heterogeneous multicore systems. In contrast to previous works, Run-DMC uses fine grain per-thread metrics that model the Thread Load Contribution (TLC) induced by the native OS scheduling policy to accurately predict performance and power for any possible thread-to-core mapping. This allows the operating system to opportunistically exploit the heterogeneous multicore architecture by dynamically mapping workloads to the most appropriate core type. We have integrated our models into the Linux kernel running on top of a heterogeneous multicore system with 4 different core types. Our experimental results show that Run-DMC models yield up to 97% more energy efficient when compared to the vanilla Linux. When compared to the approach employed by state-of-the-art energy-aware schedulers, Run-DMC yields up-to 44% better energy efficiency.
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015
Self-awareness has a long history in biology, psychology, medicine, and more recently in engineer... more Self-awareness has a long history in biology, psychology, medicine, and more recently in engineering and computing, where self-aware features are used to enable adaptivity to improve a system's functional value, performance and robustness. With complex many-core Systems-on-Chip (SoCs) facing the conflicting requirements of performance, resiliency, energy, heat, cost, security, etc. - in the face of highly dynamic operational behaviors coupled with process, environment, and workload variabilities - there is an emerging need for self-awareness in these complex SoCs. Unlike traditional MultiProcessor Systems-on-Chip (MPSoCs), self-aware SoCs must deploy an intelligent co-design of the control, communication, and computing infrastructure that interacts with the physical environment in real-time in order to modify the system's behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). Self-aware SoCs require a combination of ubiquitous sensing and actuation, health-monitoring, and statistical model-building to enable the SoC's adaptation over time and space. After defining the notion of self-awareness in computing, this paper presents the Cyber-Physical System-on-Chip (CPSoC) concept as an exemplar of a self-aware SoC that intrinsically couples on-chip and cross-layer sensing and actuation using a sensor-actuator rich fabric to enable self-awareness.
Proceedings of the 51st Annual Design Automation Conference, 2014
This paper presents a scalable and collaborative mobile crowdsensing framework for efficient coll... more This paper presents a scalable and collaborative mobile crowdsensing framework for efficient collective understanding of users, contexts, and their environments. Collaborative mobile crowdsensing enables information to be gathered and shared by users who are directly involved (participatory sensing) or integrated seamlessly as needed (opportunistic sensing) through user mobile platforms. To address the scalability needs of the mobile ecosystem, we additionally employ compressive sensing techniques for approximate gathering and processing of sensor data-this requires new mechanisms for sensor data collection, tunable approximate processing, and mobile networking architecture, to create a compressive collaborative mobile crowdsensing platform called SenseDroid. The proposed framework is build using a multi-tired hierarchical architecture to sense spatial variations of a parameter of interest, perceive spatio-temporal fields, and enable energy efficient local mobile sensing with a small number of measurements. This approximate, yet tunable approach combines different sensing approaches opportunistically while trading scalability (and coverage) for data accuracy (and energy efficiency). In this paper we propose and discuss the framework and the challenges associated with compressive and collaborative mobile sensing for multi-tired hierarchical mobile network architecture for emerging mobile collaborative applications.
Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware - ARM '12, 2012
There is a growing concern about the increasing vulnerability of future computing systems to erro... more There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware due to manufacturing process variability, exponentially increasing power dissipation and heating, as well as drastic and harsh environments such systems may have to operate in. This research proposes the concept of cross-layer virtual observers and actuations with the aim of achieving improved reliability, performance, thermal stability, and reduced power and energy consumption applied across different layers of system stack. Cross-layer resilient systems, which distribute the responsibility for tolerating errors, device variation, and aging across the system stack, have the potential to provide the resilience required to implement reliable, high-performance, low-power systems in future fabrication processes at signicantly lower cost. By using redundant, complementary, or more timely information from multiple sensors at different layers, virtual observers can provide more reliable and accurate information, specific inferences, context, and conditions as well as accurate assessment of the surrounding environment, while identifying malfunction and dangers (e.g thermal overheating or hotspot) in diverse kind of system including emerging Cyber-physical and Multiprocessor system-on-chips (MPSoCs). Virtual observer enabled self-awareness allows a system to observe it's own internal behaviors as well as external systems it interacts with such that it is capable of making judicious decision to optimize performance and other quality of service (QoS) metrics. With the ability to discover potential present action and predict future actions as well as evaluate past actions and behaviors, these computer systems will be capable of adapting their behavior and resources to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. We demonstrate the effectiveness and applicability of these concepts specifically overcoming the vulnerabilities introduced by faults and process variability using two case studies: one using virtual observer to estimate temperature of unmeasured core and the other to predict the failure rate of the unmeasured core using the estimated temperature using concepts drawn from embedded multiprocessor systems on a single chip (MPSoC) respectively.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014
This paper addresses the fundamental and practically useful question of identifying a minimum set... more This paper addresses the fundamental and practically useful question of identifying a minimum set of sensors and their locations through which a large complex dynamical network system and its time-dependent states can be observed. The paper defines the minimal sparse observability problem (MSOP) and provides analytical tools with necessary and sufficient conditions to make an arbitrary complex dynamic network system completely observable. The mathematical tools are then used to develop effective algorithms to find the sparsest measurement vector that provides the ability to estimate the internal states of a complex dynamic network system from experimentally accessible outputs. The developed algorithms are further used in the design of a sparse Kalman filter (SKF) to estimate the time-dependent internal states of a linear time-invariant (LTI) dynamical network system. The approach is applied to illustrate the minimum sensor in-situ run-time thermal estimation and robust hotspot tracking for dynamic thermal management (DTM) of high performance processors and MPSoCs.
An online, adaptive method of time delay and magnitude estimation for sinusoidal signals is prese... more An online, adaptive method of time delay and magnitude estimation for sinusoidal signals is presented. The method is based on an adaptive gradient descent algorithm that directly determines the time delay and magnitudes of two noisy sinusoidal signals. The new estimator uses a novel quadrature carrier generator to produce the carriers for an adaptive quadrature phase detector, which in turn uses an arc tan function to compute the time delay. The proposed method is quite robust and can adapt to significant variation in input signal characteristics like magnitude and frequency imposing no requirement on the magnitudes of the two signals. It even works effectively when the signals have time-varying magnitudes. The convergence analysis of the proposed technique shows that estimate converges exponentially fast to their nominal values. In addition, if the technique is implemented in the continuous time domain, the delay estimation accuracy will not be constrained by the sampling frequency...
2014 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor- and actuator-rich multiprocesso... more Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor- and actuator-rich multiprocessor system-on-chips (MPSoCs) whose operations are monitored, coordinated, and controlled using a computing-communication-control (C3) centric core with additional on-chip and cross-layer sensing and actuation capabilities that enable self-awareness within the observe-decide-act (ODA) paradigm. In order to build, evaluate, and illustrate the effectiveness of various features of this new MPSoC paradigm in a fast and cost effective way, a rapid prototyping and emulation platform along with the tool chains is absolutely necessary. In this paper, we present a design library and an FPGA emulation and prototyping platform to build and investigate self-aware adaptive computing using CPSoC paradigm. Our example implementation of CPSoC prototyping using Xilinx FPGAs includes ring-oscillator (RO) based multipurpose sensors integrated with a sensor network-on-chip (sNoC) which in turn is interfaced either to a bus based shared memory architecture or to a communication and computation network-on- chip (cNoC) distributed fabric supporting several actuation mechanism in the software and hardware stack. We also briefly discuss few applications of the CPSoC design library and the platform.
2015 28th International Conference on VLSI Design, 2015
ABSTRACT Heterogeneous multicore processors (HMP) present significant advantages over homogenous ... more ABSTRACT Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiprocessors due to their improved power, performance, and energy efficiency for a given chip/die area. However, due to their diverse and vast design space, selecting a suitable HMP configuration with different core types within a given area-power budget is an extremely challenging task. In this paper, we present a cross-layer approach for exploring and configuring a HMP for a given system goal under system level constraints (such as equal area or power budget) as an optimization problem. Unlike the state-of-the-art approaches, we jointly consider cross-layer features of the application, operating system (task allocation strategies), and hardware architecture while deploying computationally efficient predictive models (of performance and power) in configuring the HMP platform resources (number and types of cores) in an evolutionary optimization framework. Our predictive cross-layer approach enables the designer to comparatively evaluate and select the most promising (e.g., energy and performance efficient) HMP configuration in over two order of magnitude less simulation time especially during the early design and verification stages when the design space is at its largest.
Resolver sensor based angular position and speed sensing are extensively used in safety critical ... more Resolver sensor based angular position and speed sensing are extensively used in safety critical servo applications that demands accurate as well as high-resolution position and speed information for feedback control. In this paper, a novel scheme for position and speed sensing along with fault detection and identifications of a resolver sensor with systematic errors like magnitude imbalance, imperfect quadrature, and inductive harmonics is presented. The proposed scheme of resolver-to-digital (R/D) conversion mitigates the errors in position and speed estimate due to these common resolver imperfections and provides fault indicators such as good resolver signal, degradation of signal, and loss of signal for fault tolerant operation and diagnosis of malfunctions in the sensor system for safety critical systems. The proposed method incorporates software generation of the resolver carrier using a digital filter for synchronous demodulation without unintended time delay of the processed outputs, in such a way that there is substantial saving in hardware, for instance, carrier oscillator and associated digital and analog circuits for amplitude demodulators. The R/D converter incorporates an adaptive phase-locked loop (APLL) that accurately estimates the angular position and speed for a large range of operation along with superior tracking performance under dynamic conditions. Also, it provides the estimate of the magnitudes of the resolver outputs, estimate of the imperfect quadrature, and indication of harmonic distortion in the sensing angle, which can be used to directly access the quality of the resolver sensor system. Computer simulations and experimental results demonstrate an accurate R/D converter with adaptive capabilities to mitigate all the major systematic disturbances with reduced hardware complexity.
An adaptive non-linear filter (ANF) is presented that estimates and tracks the frequency, phase, ... more An adaptive non-linear filter (ANF) is presented that estimates and tracks the frequency, phase, and magnitude of an undamped as well as damped sinusoid signal. The structure of this ANF that is similar to that of a phase-locked loop (PLL), however, differs in the method of phase detection by incorporating an adaptive law to provide the phase and frequency discrimination. The stability and convergence property of this ANF is studied using Lyapunov method and is also analysed graphically using the phase plane technique to understand its behaviour and convergence properties under different conditions. It is observed that the proposed ANF, unlike PLL, provides smooth estimate of the magnitude, phase, and frequency of the input sinusoid signal and has a better noise performance. Further, the influence of the design parameters on the tracking and noise performance of the proposed ANF is also investigated. Extensive computer simulations were performed to demonstrate its effectiveness and usefulness.
Mobile phones and smartphones have evolved to be very powerful devices that have the potential to... more Mobile phones and smartphones have evolved to be very powerful devices that have the potential to be utilized in many application areas apart from generic communication. With each passing year, we see increasingly powerful smartphones being manufactured, which have a plethora of powerful embedded sensors like microphone, camera, digital compass, GPS, accelerometer, temperature sensors and many more. Moreover, the ability to easily program today's smartphones, enables us to exploit these sensors, in a wide variety of application such as personal safety, emergency and calamity response, situation awareness, remote activity monitoring, transportation and environment monitoring. In this paper, we survey the existing mobile phone sensing methodologies and application areas. We also formulate the architectural framework of our project, SenseDroid, its utility, limitations and possible future applications.
Professor Nikil Dutt, Chair Embedded systems are increasingly seeing the need for self-awareness ... more Professor Nikil Dutt, Chair Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they execute, and in the manufactured hardware. The notion of selfawareness enables a system to monitor its own state and behavior such that it is capable of making judicious decisions and adapt intelligently. However, emerging Multiprocessor Systems-on-chip (MPSoCs), used by these embedded systems and devices, still treat the elements of intelligence, specifically self-awareness, as a second-class design requirement, supporting them with ad hoc and poorly-developed awareness mechanisms, architectural supports, and system software. This dissertation overcomes these limitations by providing the foundation for a new class of self-aware adaptive MPSoCs called a Cyber-Physical-System-on-Chip (CPSoC). Unlike traditional MPSoCs, CPSoCs are distinguished by an intelligent co-design of the control, communication, and computing (C3) infrastructure while considering both the cyber and physical aspects together so as to adaptively achieve desired objectives and goals. CPSoC's sensor-actuator rich scalable architecture intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness in a principled way. The thesis corroborates, through experiments and FPGA prototypes, the key idea that giving the SoC the freedom to opportunistically adapt the software and the hardware stack by infusing self-awareness mechanisms and steerable knobs across the stack can open up new and otherwise untapped opportunities in energy efficiency, performance, and thermal resilience. xxiv
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
The increased demands of high performance, higher power/energy efficiency, and expanding function... more The increased demands of high performance, higher power/energy efficiency, and expanding functionality are moving traditional MultiProcessor Systems-on-Chips (MPSoCs) towards heterogenous many-core architectures with hundreds to thousands of cores that need to deal with a diverse and rapid stream of dynamically changing applications with competing and conflicting demands and goals. Furthermore, MPSoCs face dramatic manufacturing process variability (as semiconductor technology dives deeper into the nanometer era), and increased vulnerability to environmental and aging effects that induce errors and subsequent faults and failures. In addition, MPSoCs face vexing thermal and heating hazards, creating drastic and harsh environments (e.g., hotspots), that further aggravate aging and wearout phenomena (e.g., NBTI, HCI, TDDB, Electromigration etc. [1]) resulting in increased susceptibility to errors with the immediate consequence of diminishing yield, reliability and reduced usage lifetime [1], [2]. These new demands on MPSoC platforms with increased heterogeneity in interconnected cores result in challenging coupled/coordinated interactions, and hard to fine-tune scores of runtime parameters for sustained efficiency. Consequently, there is a critical need for improved abstraction to manage the complexity, synergistic crosslayer cooperation and adaptations to effectively manage the onchip resources, and new means of actuations and actions to meet the aggressive and competing demands/goals. Additionally, MPSoCs need to sense many more physical phenomena and system states across multiple abstraction levels in order to exploit workload and process variabilities [1], find root causes of faults and failures, as well as identify vulnerabilities (e.g. thermal hotspots, malicious attacks) to take proactive actions. To address these challenges, we present CyberPhysical-Systemson-Chip (CPSoC) [3], a new class of sensor-actuator rich many-core computing platforms that intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness (Figure 1). Unlike traditional MPSoC designs, the CPSoC paradigm co-designs the control, communication, and computing (C3) system that interacts with the physical environment in real-time to modify the system's behavior [4] so as to adaptively achieve desired objectives and Quality-of-Service (QoS). The CPSoC design paradigm enables selfawareness [5] (i.e., the ability of the system to observe its own
The task of architectural Design Space Exploration (DSE) is extremely complex, with multiple arch... more The task of architectural Design Space Exploration (DSE) is extremely complex, with multiple architectural parameters to be tuned and optimized, resulting in a huge design space that needs to be explored efficiently. Furthermore, each architectural parameter and/or design point is critically affected by decisions made at lower levels of abstraction (e.g., layout, choice of transistors, etc.). Ideally designers would like to perform DSE incorporating information and decisions made across multiple layers of design abstraction so that the ensuing design space is both feasible and has good fidelity. Simulation-based methods alone can not deal with this incredibly large and complex design space. To address these issues, this chapter presents an approach for cross-layer architectural DSE that efficiently prunes the large design space and furthermore uses predictive models to avoid expensive simulations. The chapter uses a singlechip heterogeneous single-ISA multiprocessor as an exemplar to demonstrate how the large search space can be covered and evaluated efficiently. A crosslayer approach is presented to cope with the complexity by restricting the search/design space through the use of cross-layer prediction models to avoid too costly full system simulations, coupled with systematic pruning of the design space to enable good coverage of the design space in an efficient manner.
Author(s): Sarma, Santanu | Advisor(s): Dutt, Nikil | Abstract: This thesis presents an efficient... more Author(s): Sarma, Santanu | Advisor(s): Dutt, Nikil | Abstract: This thesis presents an efficient and scalable sense-making framework using machine learning techniques for Internet-of-Things (IoTs) in order to understand users, contexts, and their environments to make meaningful decisions. The proposed sense-making IoT framework, called Essence, employs combination of participatory mobile crowdsensing along with infrastructure sensing to perform sense-making using machine learning techniques. While collaborative mobile crowdsensing enables information to be gathered and shared by users who are directly involved (participatory sensing) or integrated seamlessly as needed (opportunistic sensing) through user mobile platforms, the infrastructure sensing fabric of the Essence framework provides sense-making support for scenarios where mobile sensing platforms are inadequate. To address the scalability needs of the Essence framework, we employ dimensionality reduction techniques such as p...
Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiproc... more Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiprocessor due to their improved power, performance, and energy efficiency for a given chip/die area. However, to fully tap their potential, a systematic exploration of their diverse and vast design space is necessary. In this paper, we present a cross-layer (across application, operating system, and hardware architecture layer) design space exploration (DSE) of single-ISA (Instruction Set Architecture) heterogeneous multicore processors. We deploy predictive models to investigate the interactions and influence of heterogeneity (configurations, number and types of cores), multiobjective allocation strategies, along with diverse types of workloads under system level constraints (such as equal area or power budget). We perform a cross-layer DSE study of heterogeneous multicore processors with four simulated annealing (SA) based task allocation strategies that are more generic and efficient in c...
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
To meet the performance and energy efficiency demands of emerging complex and variable workloads,... more To meet the performance and energy efficiency demands of emerging complex and variable workloads, heterogeneous manycore architectures are increasingly being deployed, necessitating operating systems support for adaptive task allocation to efficiently exploit this heterogeneity in the face of unpredictable workloads. We present SPARTA, a throughput-aware runtime task allocation approach for Heterogeneous manycore Platforms (HMPs) to achieve energy efficiency. SPARTA collects sensor data to characterize tasks at runtime and uses this information to prioritize tasks when performing allocation in order to maximize energy-efficiency (instructions-per-Joule) without sacrificing performance. Our experimental results on heterogeneous manycore architectures executing mixes of MiBench and PARSEC benchmarks demonstrate energy reductions of up to 23% when compared to state-of-the-art alternatives. SPARTA is also scalable with low overhead, enabling energy savings in large-scale architectures with up to hundreds of cores.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
Cyber-physical systems (CPSs) are physical and engineered systems whose operations are monitored,... more Cyber-physical systems (CPSs) are physical and engineered systems whose operations are monitored, coordinated, controlled, and integrated by a computing, control, and communication core. We propose Cyberphysical-System-on-Chip (CPSoC), a new class of sensor and actuator-rich multiprocessor systemson-chip (MPSoCs), that augment MPSoCs with additional onchip and cross-layer sensing and actuation capabilities to enable self-awareness within the observe-decide-act (ODA) paradigm. Unlike traditional MPSoC designs, CPSoC differs primarily on the co-design of computing-communication-control (C3) systems that interacts with the physical environment in real-time in order to adapt system behavior so as to dynamically react to environmental changes while achieving overall design goals. We illustrate CPSoC's potential through a virtual sensor network that accurately estimates run-time power for variability affected subsystems using noisy thermal sensors in improving system goals and Quality-of-Service (QoS).
Australian Journal of Electrical and Electronics Engineering, 2008
Abstract Three adaptive frequency and phase-locked loops (referred as APLL, APLL1, and APLL2) are... more Abstract Three adaptive frequency and phase-locked loops (referred as APLL, APLL1, and APLL2) are presented that uses a modified phase detector for improved performance. These adaptive phase-locked loops (PLL) have considerably superior performance compared to the conventional and Costas PLL in terms of convergence speed, tracking quality, and frequency acquisition range as well as acquisition time under dynamic conditions. The stability and convergence properties of these three adaptive PLLs are studied using Lyapunov methods. Further, the influence of the design parameters on the tracking and noise performance of these PLLs are shown. Unlike conventional PLL, these adaptive PLL have lesser phase and frequency variance and provides smooth estimates of the frequency, phase, and magnitude of the input sinusoid signal. They are also computationally less expensive than the conventional and Costas PLL as there is no need for an additional low pass filter after the multiplier phase detector. Extensive computer simulations are performed to compare and demonstrate their effectiveness for different conditions. Simulation results show that all the three adaptive PLLs outperform conventional and Costas PLL in terms of frequency estimate accuracy and frequency acquisition range. In addition, it is observed from the simulation results that APPL2 has better performance compared the other PLLs in terms of tracking speed, accuracy, and frequency range.
2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2015
In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for... more In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for dynamic workloads executing on heterogeneous multicore systems. In contrast to previous works, Run-DMC uses fine grain per-thread metrics that model the Thread Load Contribution (TLC) induced by the native OS scheduling policy to accurately predict performance and power for any possible thread-to-core mapping. This allows the operating system to opportunistically exploit the heterogeneous multicore architecture by dynamically mapping workloads to the most appropriate core type. We have integrated our models into the Linux kernel running on top of a heterogeneous multicore system with 4 different core types. Our experimental results show that Run-DMC models yield up to 97% more energy efficient when compared to the vanilla Linux. When compared to the approach employed by state-of-the-art energy-aware schedulers, Run-DMC yields up-to 44% better energy efficiency.
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015
Self-awareness has a long history in biology, psychology, medicine, and more recently in engineer... more Self-awareness has a long history in biology, psychology, medicine, and more recently in engineering and computing, where self-aware features are used to enable adaptivity to improve a system's functional value, performance and robustness. With complex many-core Systems-on-Chip (SoCs) facing the conflicting requirements of performance, resiliency, energy, heat, cost, security, etc. - in the face of highly dynamic operational behaviors coupled with process, environment, and workload variabilities - there is an emerging need for self-awareness in these complex SoCs. Unlike traditional MultiProcessor Systems-on-Chip (MPSoCs), self-aware SoCs must deploy an intelligent co-design of the control, communication, and computing infrastructure that interacts with the physical environment in real-time in order to modify the system's behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). Self-aware SoCs require a combination of ubiquitous sensing and actuation, health-monitoring, and statistical model-building to enable the SoC's adaptation over time and space. After defining the notion of self-awareness in computing, this paper presents the Cyber-Physical System-on-Chip (CPSoC) concept as an exemplar of a self-aware SoC that intrinsically couples on-chip and cross-layer sensing and actuation using a sensor-actuator rich fabric to enable self-awareness.
Proceedings of the 51st Annual Design Automation Conference, 2014
This paper presents a scalable and collaborative mobile crowdsensing framework for efficient coll... more This paper presents a scalable and collaborative mobile crowdsensing framework for efficient collective understanding of users, contexts, and their environments. Collaborative mobile crowdsensing enables information to be gathered and shared by users who are directly involved (participatory sensing) or integrated seamlessly as needed (opportunistic sensing) through user mobile platforms. To address the scalability needs of the mobile ecosystem, we additionally employ compressive sensing techniques for approximate gathering and processing of sensor data-this requires new mechanisms for sensor data collection, tunable approximate processing, and mobile networking architecture, to create a compressive collaborative mobile crowdsensing platform called SenseDroid. The proposed framework is build using a multi-tired hierarchical architecture to sense spatial variations of a parameter of interest, perceive spatio-temporal fields, and enable energy efficient local mobile sensing with a small number of measurements. This approximate, yet tunable approach combines different sensing approaches opportunistically while trading scalability (and coverage) for data accuracy (and energy efficiency). In this paper we propose and discuss the framework and the challenges associated with compressive and collaborative mobile sensing for multi-tired hierarchical mobile network architecture for emerging mobile collaborative applications.
Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware - ARM '12, 2012
There is a growing concern about the increasing vulnerability of future computing systems to erro... more There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware due to manufacturing process variability, exponentially increasing power dissipation and heating, as well as drastic and harsh environments such systems may have to operate in. This research proposes the concept of cross-layer virtual observers and actuations with the aim of achieving improved reliability, performance, thermal stability, and reduced power and energy consumption applied across different layers of system stack. Cross-layer resilient systems, which distribute the responsibility for tolerating errors, device variation, and aging across the system stack, have the potential to provide the resilience required to implement reliable, high-performance, low-power systems in future fabrication processes at signicantly lower cost. By using redundant, complementary, or more timely information from multiple sensors at different layers, virtual observers can provide more reliable and accurate information, specific inferences, context, and conditions as well as accurate assessment of the surrounding environment, while identifying malfunction and dangers (e.g thermal overheating or hotspot) in diverse kind of system including emerging Cyber-physical and Multiprocessor system-on-chips (MPSoCs). Virtual observer enabled self-awareness allows a system to observe it's own internal behaviors as well as external systems it interacts with such that it is capable of making judicious decision to optimize performance and other quality of service (QoS) metrics. With the ability to discover potential present action and predict future actions as well as evaluate past actions and behaviors, these computer systems will be capable of adapting their behavior and resources to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. We demonstrate the effectiveness and applicability of these concepts specifically overcoming the vulnerabilities introduced by faults and process variability using two case studies: one using virtual observer to estimate temperature of unmeasured core and the other to predict the failure rate of the unmeasured core using the estimated temperature using concepts drawn from embedded multiprocessor systems on a single chip (MPSoC) respectively.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014
This paper addresses the fundamental and practically useful question of identifying a minimum set... more This paper addresses the fundamental and practically useful question of identifying a minimum set of sensors and their locations through which a large complex dynamical network system and its time-dependent states can be observed. The paper defines the minimal sparse observability problem (MSOP) and provides analytical tools with necessary and sufficient conditions to make an arbitrary complex dynamic network system completely observable. The mathematical tools are then used to develop effective algorithms to find the sparsest measurement vector that provides the ability to estimate the internal states of a complex dynamic network system from experimentally accessible outputs. The developed algorithms are further used in the design of a sparse Kalman filter (SKF) to estimate the time-dependent internal states of a linear time-invariant (LTI) dynamical network system. The approach is applied to illustrate the minimum sensor in-situ run-time thermal estimation and robust hotspot tracking for dynamic thermal management (DTM) of high performance processors and MPSoCs.
An online, adaptive method of time delay and magnitude estimation for sinusoidal signals is prese... more An online, adaptive method of time delay and magnitude estimation for sinusoidal signals is presented. The method is based on an adaptive gradient descent algorithm that directly determines the time delay and magnitudes of two noisy sinusoidal signals. The new estimator uses a novel quadrature carrier generator to produce the carriers for an adaptive quadrature phase detector, which in turn uses an arc tan function to compute the time delay. The proposed method is quite robust and can adapt to significant variation in input signal characteristics like magnitude and frequency imposing no requirement on the magnitudes of the two signals. It even works effectively when the signals have time-varying magnitudes. The convergence analysis of the proposed technique shows that estimate converges exponentially fast to their nominal values. In addition, if the technique is implemented in the continuous time domain, the delay estimation accuracy will not be constrained by the sampling frequency...
2014 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor- and actuator-rich multiprocesso... more Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor- and actuator-rich multiprocessor system-on-chips (MPSoCs) whose operations are monitored, coordinated, and controlled using a computing-communication-control (C3) centric core with additional on-chip and cross-layer sensing and actuation capabilities that enable self-awareness within the observe-decide-act (ODA) paradigm. In order to build, evaluate, and illustrate the effectiveness of various features of this new MPSoC paradigm in a fast and cost effective way, a rapid prototyping and emulation platform along with the tool chains is absolutely necessary. In this paper, we present a design library and an FPGA emulation and prototyping platform to build and investigate self-aware adaptive computing using CPSoC paradigm. Our example implementation of CPSoC prototyping using Xilinx FPGAs includes ring-oscillator (RO) based multipurpose sensors integrated with a sensor network-on-chip (sNoC) which in turn is interfaced either to a bus based shared memory architecture or to a communication and computation network-on- chip (cNoC) distributed fabric supporting several actuation mechanism in the software and hardware stack. We also briefly discuss few applications of the CPSoC design library and the platform.
2015 28th International Conference on VLSI Design, 2015
ABSTRACT Heterogeneous multicore processors (HMP) present significant advantages over homogenous ... more ABSTRACT Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiprocessors due to their improved power, performance, and energy efficiency for a given chip/die area. However, due to their diverse and vast design space, selecting a suitable HMP configuration with different core types within a given area-power budget is an extremely challenging task. In this paper, we present a cross-layer approach for exploring and configuring a HMP for a given system goal under system level constraints (such as equal area or power budget) as an optimization problem. Unlike the state-of-the-art approaches, we jointly consider cross-layer features of the application, operating system (task allocation strategies), and hardware architecture while deploying computationally efficient predictive models (of performance and power) in configuring the HMP platform resources (number and types of cores) in an evolutionary optimization framework. Our predictive cross-layer approach enables the designer to comparatively evaluate and select the most promising (e.g., energy and performance efficient) HMP configuration in over two order of magnitude less simulation time especially during the early design and verification stages when the design space is at its largest.
Resolver sensor based angular position and speed sensing are extensively used in safety critical ... more Resolver sensor based angular position and speed sensing are extensively used in safety critical servo applications that demands accurate as well as high-resolution position and speed information for feedback control. In this paper, a novel scheme for position and speed sensing along with fault detection and identifications of a resolver sensor with systematic errors like magnitude imbalance, imperfect quadrature, and inductive harmonics is presented. The proposed scheme of resolver-to-digital (R/D) conversion mitigates the errors in position and speed estimate due to these common resolver imperfections and provides fault indicators such as good resolver signal, degradation of signal, and loss of signal for fault tolerant operation and diagnosis of malfunctions in the sensor system for safety critical systems. The proposed method incorporates software generation of the resolver carrier using a digital filter for synchronous demodulation without unintended time delay of the processed outputs, in such a way that there is substantial saving in hardware, for instance, carrier oscillator and associated digital and analog circuits for amplitude demodulators. The R/D converter incorporates an adaptive phase-locked loop (APLL) that accurately estimates the angular position and speed for a large range of operation along with superior tracking performance under dynamic conditions. Also, it provides the estimate of the magnitudes of the resolver outputs, estimate of the imperfect quadrature, and indication of harmonic distortion in the sensing angle, which can be used to directly access the quality of the resolver sensor system. Computer simulations and experimental results demonstrate an accurate R/D converter with adaptive capabilities to mitigate all the major systematic disturbances with reduced hardware complexity.
An adaptive non-linear filter (ANF) is presented that estimates and tracks the frequency, phase, ... more An adaptive non-linear filter (ANF) is presented that estimates and tracks the frequency, phase, and magnitude of an undamped as well as damped sinusoid signal. The structure of this ANF that is similar to that of a phase-locked loop (PLL), however, differs in the method of phase detection by incorporating an adaptive law to provide the phase and frequency discrimination. The stability and convergence property of this ANF is studied using Lyapunov method and is also analysed graphically using the phase plane technique to understand its behaviour and convergence properties under different conditions. It is observed that the proposed ANF, unlike PLL, provides smooth estimate of the magnitude, phase, and frequency of the input sinusoid signal and has a better noise performance. Further, the influence of the design parameters on the tracking and noise performance of the proposed ANF is also investigated. Extensive computer simulations were performed to demonstrate its effectiveness and usefulness.
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Papers by Santanu Sarma