Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
Previous research in the area o f b ehavioral synthesis of digital circuits has mostly concentrat... more Previous research in the area o f b ehavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault eects from module outputs to system outputs. Genesis provided 100% system-level testability for all the synthesized b enchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an ecient gate-level sequential test generator. The area overhead of circuits synthesized b y Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability. Genesis can also easily handle loop constructs in the behavioral specication.
IEICE Transactions on Information and Systems, 2010
This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set ... more This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests (MISR-bypass test mode) while achieving ultimate output compression using MISRs for the majority of tests (MISR-enabled test mode.) By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support compression mode volume diagnostics. In our experiment, the MISR-bypass test was first executed and at 10% of the total test set the MISR-enabled test was performed. The results show that compared with MISR+XOR-based compression the proposed technique provides better volume diagnosis with slightly small (0.71 X to 0.97 X) compaction ratio. The scan cycles are about the same as the MISRenabled mode. A possible application to partial good chips is also shown.
In this paper test compaction techniques suitable for circuits designed using a novel parallel ac... more In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-inlout operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.
A unifying methodology for intellectual property and custom logic testing
Proceedings International Test Conference 1996. Test and Design Validity
... For IP blocks with more ports than chip pins, the use of an LFSR on the IP outputs allows re-... more ... For IP blocks with more ports than chip pins, the use of an LFSR on the IP outputs allows re-use of IP test vectors and ... in this paper allows the use of a partial test grid approach, analogous to partial scan, in which not all of the storage elements are re-configurable as matrix ...
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
Previous research in the area o f b ehavioral synthesis of digital circuits has mostly concentrat... more Previous research in the area o f b ehavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault eects from module outputs to system outputs. Genesis provided 100% system-level testability for all the synthesized b enchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an ecient gate-level sequential test generator. The area overhead of circuits synthesized b y Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability. Genesis can also easily handle loop constructs in the behavioral specication.
IEICE Transactions on Information and Systems, 2010
This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set ... more This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests (MISR-bypass test mode) while achieving ultimate output compression using MISRs for the majority of tests (MISR-enabled test mode.) By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support compression mode volume diagnostics. In our experiment, the MISR-bypass test was first executed and at 10% of the total test set the MISR-enabled test was performed. The results show that compared with MISR+XOR-based compression the proposed technique provides better volume diagnosis with slightly small (0.71 X to 0.97 X) compaction ratio. The scan cycles are about the same as the MISRenabled mode. A possible application to partial good chips is also shown.
In this paper test compaction techniques suitable for circuits designed using a novel parallel ac... more In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-inlout operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.
A unifying methodology for intellectual property and custom logic testing
Proceedings International Test Conference 1996. Test and Design Validity
... For IP blocks with more ports than chip pins, the use of an LFSR on the IP outputs allows re-... more ... For IP blocks with more ports than chip pins, the use of an LFSR on the IP outputs allows re-use of IP test vectors and ... in this paper allows the use of a partial test grid approach, analogous to partial scan, in which not all of the storage elements are re-configurable as matrix ...
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Papers by Sandeep Bhatia