Papers by Sampath Kumar V
IEEE Access
The article presents the design and development of invasive weed optimization (IWO) for the senso... more The article presents the design and development of invasive weed optimization (IWO) for the sensor less speed control of doubly fed induction generator (DFIG) under balanced and unbalanced conditions. A healthy condition represents the balanced condition while unbalancing condition is characterized by unhealthy conditions like three-phase fault, single line to ground fault, the line-to-line fault, and double line to ground fault. The DFIG is driven by wind and integrated with the grid. The advantages associated with IWO technique are a simple mathematical approach and less data computation. Normally, DFIG consists of two back-to-back converters namely grid side converter (GSC) and rotor side converter (RSC). The GSC is an uncontrolled converter while the RSC is a controlled converter. The existing methods have poor performance parameters like settling time, peak overshoot for balanced conditions, and poor power quality parameters like total harmonic distortion (THD) for unbalanced conditions. An IWO technique has been applied to overcome such limitations. The effectiveness of the sensor less speed control is also analyzed with other techniques like Adaptive Neuro-Fuzzy Interference System (AN-FIS) & artificial neural network (ANN). The design of ANN is based on the feed-forward method using back propagation delay and the design of ANFIS is based on adaptive control and state space control strategy. It is observed that performance parameters like peak overshoot and settling time for the sensor less speed of DFIG are found to be more profound with IWO in comparison to ANFIS, ANN, and other existing techniques for balanced conditions. Similarly in the unbalanced condition, faulty current approaches are quite closer to their healthy state with the IWO method in comparison to other methods. In addition to this, minimum distortion (%THD) for the grid current under unbalanced conditions is also attained with IWO in comparison to ANFIS, ANN, and other existing techniques. Such application of IWO makes the system highly efficient and robust.
This paper deals with the design & analysis of Carry Select Adder (CSLA) & Carry lookahead adder ... more This paper deals with the design & analysis of Carry Select Adder (CSLA) & Carry lookahead adder (CLA). Adders are designed using 0.18µm CMOS process technology & simulated with Modelsim6.3f. The adder designs, Regular CSLA, modified CSLA using BEC, modified CSLA without using multiplexer, modified CSLA using D-Latch & Carry lookahead adders in 4-bit, 16-bit, 32-bit, are compared with the simulated results on the basis area.
Over the past decade, several adiabatic logic styles have been reported. This paper deals with th... more Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using several adiabatic logic styles, which are derived from static CMOS logic, without a large change. The full adders are designed using 180nm technology parameters provided by predictive technology and simulated using HSPICE. The full adders designed are compared in terms of average power consumption with different values of load capacitance, temperature and input frequency. The different designs of full adder are also compared on the basis of propagation delay exhibit by them. It is found that, full adders designed with adiabatic logic styles tends to consume very low power in comparison to full adder designed with static CMOS logic. Under certain operating conditions, one of adiabatic designs of full adder achieves upto 74% power saving in comparison to the full adder designed with static CMOS logic.
International Journal of VLSI Design & Communication Systems, 2011
As in today's date fuel consumption is important in everything from scooters to oil tankers, powe... more As in today's date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs. The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.
International Journal for Scientific Research and Development, 2015
In high-speed high-resolution analog to digital converters, comparators have a key role in qualit... more In high-speed high-resolution analog to digital converters, comparators have a key role in quality of performance. High power consumption is one of the drawbacks of these circuits which can be reduced by using suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron design technologies. The selection of particular topology is dependent upon the requirements and applications of the design. Low power and high speed circuit design has emerged as a principal theme in today’s electronics industry. In this paper, a basic SA-ADC (successive approximation) is discussed as a proper choice for low power applications and comparison with other ADC architectures. Following with the study of design parameters of comparator, their architectures and its use in various applications.
Journal of Engineering Education Transformations
Competency based education and its continuous assessment creates a strong interest amongst all st... more Competency based education and its continuous assessment creates a strong interest amongst all stakeholders involved in the laboratories. The initiatives in this paper are proposed to strengthen affiliating technical university curriculum in true spirit to adopt outcome-based (OBE) education practices at all levels of courses. These initiatives shall complement and supplement the Government of India initiative National Education Policy 2020 (NEP 2020) implementation. The main beneficiaries of this proposed work will be the students and faculty among important stakeholders. The initiatives proposed will help to ease the problems of identifying proper learning materials, identification of course pre-requisites, and for the effective Industry Academia Connect for better development of employable graduates with Industry required attributes and skills. Also, to ensure highest standards of Teaching -Learning experience which will lead towards academic excellence, ensures to become an acti...
Power gating and its repercussions—a review
2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), 2016
In this paper, Power gating/ Multithreshold technique for low power circuit design is summarized ... more In this paper, Power gating/ Multithreshold technique for low power circuit design is summarized and compared. Few important and vital parameters such as sizing of sleep transistor, mode transition energy, reduction of noise due to ground bounce, area, delay and noise margin are compared for different techniques. In charge recycling technique upto 43% of mode transition energy is saved and an average of 8.25%, 33.1% of reduction in positive and negative peak ground bounce is obtained respectively. Bin-Packaging technique for clustering gives more leakage saving (84%) with respect to cell-partitioning technique. Considering overall response, Dynamic forward body bias triode MTCMOS technique (DFBBL) is found to be the best for sequential circuit (32-bit shift register) and for combinational circuit (32-bit Brent kung adder), triple phase technique gives the best response. Digital triple phase technique improves the overall electrical quality by 9.15 times and overall tolerance to parameter variations by 183.1 times as compared to other slew rate modulation techniques. DFBBL technique gives ground bounce reduction upto 90% and it also reduces the active power consumption about 47.3%. The data stability of sequential circuits is improved by 16.92%.
Low power technique in domino logic circuit
2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), 2015
High performance circuits demands domino logic design. A new technique for reducing the power con... more High performance circuits demands domino logic design. A new technique for reducing the power consumption and increasing the speed without effecting noise margin is reviewed in this paper. In this technique threshold voltage of the keeper transistor is varied using body bias generator circuit. Three different body bias generator circuits are simulated, they are dynamic body bias generator, capacitive body bias generator and cross couple capacitive body bias generator circuit. Simulations are performed on tanner EDA tool at 180 nm and 65nm technology, for carry look ahead adder. The simulation results show that CBBG and CCCBBG have reduced power consumption and delay in comparison to other circuit techniques.
Analysis of high speed CMOS current comparator is presented with low input impedance using a simp... more Analysis of high speed CMOS current comparator is presented with low input impedance using a simple biasing method. The simulation results from PSPICE demonstrate the propagation delay at low input currents at supply voltages of 1.8v, 2v, 2. 2v and stability analysis using 0.25um CMOS technology. So it is suitable to high speed applications.
Uploads
Papers by Sampath Kumar V