Recent advances in the field of Novel drug delivery systems have gained scientist attention to de... more Recent advances in the field of Novel drug delivery systems have gained scientist attention to develop orodispersible tablets in order to enhance safety and efficacy of the drug. Osteoporosis is a diseases of bones which occurs due to lack of protein and minerals particularly calcium in bones. Presently available dosage forms lack to produce desired therapeutic effect. Orodispersible tablets of Risedronate sodium which helps in producing desired therapeutic effect within fraction of minutes. Risedronate sodium that inhibits osteoclast-mediated bone resorption and modulates bone metabolism. This has encouraged in the field of industry to develop new disintegrating formulations. The main aim of this article is to develop new ODT technologies and evaluation methodologies in order to enhance patient compliance.
International Journal Of Engineering And Computer Science, 2016
In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for ... more In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for multimedia applications. This paper Implemented conventional DCT and multiplier less DCT"s by less number of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations. Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared to conventional DCT. Power delay product of both conventional DCT and multiplier less DCT"s are 19.8mJ, 19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadence RTL compiler 180nm.
In the LTE, OFDM is the multicarrier technology used for the downlink data transmission of the mu... more In the LTE, OFDM is the multicarrier technology used for the downlink data transmission of the multicarrier signal. OFDM (orthogonal frequency division multiplexing) the main well known drawback is peak average power ratio (PAPR). Due to the increase in the PAPR the power amplifier of the transmission must be operated in high back-off region in order to be in the linear region. The system efficiency will be decreased so PAPR is considered as the primary concern to be eliminated.PTS is the technique used for the reduction of PAPR. The PTS(partial transmit sequence) has the high complexity factor in IFFT and FFT computations , this paper gives the study of the PAPR with modified partial transmit sequence and the complexity of the PTS has been reduced by using the artificial bee algorithm(ABC). The desired PAPR can be achieved by using the noise shaping , this reduction technique is performed by using 16QAM , with 2048 subcarriers having the block size of 4 different phase factors a 4.1db PAPR reduction at 4 10 − complementary cumulative distribution function (CCDF) level and EVM of 6% is achieved.
Abstrac t: Over the past two decades, there have been various studies on the distributions of the... more Abstrac t: Over the past two decades, there have been various studies on the distributions of the discrete cosine transformat ion (DCT). The main objective of this work is to explore one of various architectures for optimizing any one or all of the given constraints (speed, power). Given these constraints (speed, power) this architecture will be a best suited as per the requirement. DCT is implem ented using different methods i.e. conventional DCT and Fast-DCT. DCT algorith ms are consistence mult ipliers and adders, this implementation necessitate more area, slo w software and it consume more power. To overco me these limitations and attain faste r, instead of mult iplications distributed algorithm (DA) is being used. The architectures are designed and imp lemented in VERILOG and synthesized in Xilin x tools, which makes the number of adders used in fast-DCT implementation reduced by 64.8% and mu ltip liers are reduced by 77.2%. Keywords: fast – Discrete Cosine Transformation (DCT), conventional Discrete Cosine Transformat ion (DCT), distributed algorith m (DA). I. INTRODUCTION The recent expansion of image co mpression mult imedia based applications associated with new technologies. These technologies has increased the need for more powerful algorith ms to satisfy the requirement, now a day's many wireless communicat ions such as digital camera, mult imedia mobiles and handheld devices suffer fro m both limited memo ry and power resources. The trends of fast discrete cosine transform have become impo rtant due to the increasing wireless technology. To avoid these limitations proposed fast discrete cosine transformation (Fast-DCT). Fast-DCT algorith ms present a number of modifications to the basic DCT architecture; each of these modifications could solve certain limitations and therefore improve and ease to imp lement. Conventional DCT imp lementation is computational burden due to number of mu ltip liers and additions. In this paper multiplier less architecture, such as distributed arithmetic is used to improve speed, power consumption. This paper proposes fast-DCT architecture for image compression. The proposed architecture is designed to reduce the number of mu ltipliers used in conventional DCT. So many fast-DCT algorith ms have been implemented [1– 2]. In this paper instead of mult iplications distributed algorithm is being used. The main advantage of distributed algorithm is to speed up the multiplication process by pre computation [3]. The proposed and conventional DCT architecture are implemented on Xilin x. Th is paper is organized as follows. Section II involves conventional DCT and fast DCT algorith m imp lementation. Co mparison and discussion involves in section III and conclusion discussed in the last section.
In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for ... more In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for multimedia applications. This paper Implemented conventional DCT and multiplier less DCT " s by less number of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations. Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared to conventional DCT. Power delay product of both conventional DCT and multiplier less DCT " s are 19.8mJ, 19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadence RTL compiler 180nm.
In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transfor... more In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transform (DCT) Algorithm, which process data in a sequential form at high data rate. We designed a novel DCT by using orthogonal property and compared with conventional DCT in terms of number of cells, cell area, leakage power, internal power, net power, switching power, delay and power delay product (PDP). In comparison with multiplier based conventional DCT and Adder based Conventional DCT, the net power dissipation is reduced by 32%. The proposed Adder based DCT net power Dissipation is reduced by 47% less and multiplier based proposed DCT is reduced by 38%. Here we have used Cadence RTL 180nm Technology to implement the design.
A 5-bit flash analog to digital converter (ADC) is implemented on 180nm CMOS technology. The ADC ... more A 5-bit flash analog to digital converter (ADC) is implemented on 180nm CMOS technology. The ADC is operates at 1.2v and employs best comparator to improve performance of ADC. In this paper implemented two types of comparators, latch type comparator and proposed comparator. Dual input single output differential amplifier as latch stage has been used in proposed comparator. The simulation result of ADC is operating at 5GHz sampling frequency and its delay and power dissipation is 419.9ns and 15.2 mw respectively. At 5GHz the average power dissipation of the encoder circuit is 58.5uw and delay 1.29 ns and proposed comparator delay is 1.1ns.
Recent advances in the field of Novel drug delivery systems have gained scientist attention to de... more Recent advances in the field of Novel drug delivery systems have gained scientist attention to develop orodispersible tablets in order to enhance safety and efficacy of the drug. Osteoporosis is a diseases of bones which occurs due to lack of protein and minerals particularly calcium in bones. Presently available dosage forms lack to produce desired therapeutic effect. Orodispersible tablets of Risedronate sodium which helps in producing desired therapeutic effect within fraction of minutes. Risedronate sodium that inhibits osteoclast-mediated bone resorption and modulates bone metabolism. This has encouraged in the field of industry to develop new disintegrating formulations. The main aim of this article is to develop new ODT technologies and evaluation methodologies in order to enhance patient compliance.
International Journal Of Engineering And Computer Science, 2016
In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for ... more In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for multimedia applications. This paper Implemented conventional DCT and multiplier less DCT"s by less number of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations. Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared to conventional DCT. Power delay product of both conventional DCT and multiplier less DCT"s are 19.8mJ, 19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadence RTL compiler 180nm.
In the LTE, OFDM is the multicarrier technology used for the downlink data transmission of the mu... more In the LTE, OFDM is the multicarrier technology used for the downlink data transmission of the multicarrier signal. OFDM (orthogonal frequency division multiplexing) the main well known drawback is peak average power ratio (PAPR). Due to the increase in the PAPR the power amplifier of the transmission must be operated in high back-off region in order to be in the linear region. The system efficiency will be decreased so PAPR is considered as the primary concern to be eliminated.PTS is the technique used for the reduction of PAPR. The PTS(partial transmit sequence) has the high complexity factor in IFFT and FFT computations , this paper gives the study of the PAPR with modified partial transmit sequence and the complexity of the PTS has been reduced by using the artificial bee algorithm(ABC). The desired PAPR can be achieved by using the noise shaping , this reduction technique is performed by using 16QAM , with 2048 subcarriers having the block size of 4 different phase factors a 4.1db PAPR reduction at 4 10 − complementary cumulative distribution function (CCDF) level and EVM of 6% is achieved.
Abstrac t: Over the past two decades, there have been various studies on the distributions of the... more Abstrac t: Over the past two decades, there have been various studies on the distributions of the discrete cosine transformat ion (DCT). The main objective of this work is to explore one of various architectures for optimizing any one or all of the given constraints (speed, power). Given these constraints (speed, power) this architecture will be a best suited as per the requirement. DCT is implem ented using different methods i.e. conventional DCT and Fast-DCT. DCT algorith ms are consistence mult ipliers and adders, this implementation necessitate more area, slo w software and it consume more power. To overco me these limitations and attain faste r, instead of mult iplications distributed algorithm (DA) is being used. The architectures are designed and imp lemented in VERILOG and synthesized in Xilin x tools, which makes the number of adders used in fast-DCT implementation reduced by 64.8% and mu ltip liers are reduced by 77.2%. Keywords: fast – Discrete Cosine Transformation (DCT), conventional Discrete Cosine Transformat ion (DCT), distributed algorith m (DA). I. INTRODUCTION The recent expansion of image co mpression mult imedia based applications associated with new technologies. These technologies has increased the need for more powerful algorith ms to satisfy the requirement, now a day's many wireless communicat ions such as digital camera, mult imedia mobiles and handheld devices suffer fro m both limited memo ry and power resources. The trends of fast discrete cosine transform have become impo rtant due to the increasing wireless technology. To avoid these limitations proposed fast discrete cosine transformation (Fast-DCT). Fast-DCT algorith ms present a number of modifications to the basic DCT architecture; each of these modifications could solve certain limitations and therefore improve and ease to imp lement. Conventional DCT imp lementation is computational burden due to number of mu ltip liers and additions. In this paper multiplier less architecture, such as distributed arithmetic is used to improve speed, power consumption. This paper proposes fast-DCT architecture for image compression. The proposed architecture is designed to reduce the number of mu ltipliers used in conventional DCT. So many fast-DCT algorith ms have been implemented [1– 2]. In this paper instead of mult iplications distributed algorithm is being used. The main advantage of distributed algorithm is to speed up the multiplication process by pre computation [3]. The proposed and conventional DCT architecture are implemented on Xilin x. Th is paper is organized as follows. Section II involves conventional DCT and fast DCT algorith m imp lementation. Co mparison and discussion involves in section III and conclusion discussed in the last section.
In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for ... more In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for multimedia applications. This paper Implemented conventional DCT and multiplier less DCT " s by less number of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations. Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared to conventional DCT. Power delay product of both conventional DCT and multiplier less DCT " s are 19.8mJ, 19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadence RTL compiler 180nm.
In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transfor... more In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transform (DCT) Algorithm, which process data in a sequential form at high data rate. We designed a novel DCT by using orthogonal property and compared with conventional DCT in terms of number of cells, cell area, leakage power, internal power, net power, switching power, delay and power delay product (PDP). In comparison with multiplier based conventional DCT and Adder based Conventional DCT, the net power dissipation is reduced by 32%. The proposed Adder based DCT net power Dissipation is reduced by 47% less and multiplier based proposed DCT is reduced by 38%. Here we have used Cadence RTL 180nm Technology to implement the design.
A 5-bit flash analog to digital converter (ADC) is implemented on 180nm CMOS technology. The ADC ... more A 5-bit flash analog to digital converter (ADC) is implemented on 180nm CMOS technology. The ADC is operates at 1.2v and employs best comparator to improve performance of ADC. In this paper implemented two types of comparators, latch type comparator and proposed comparator. Dual input single output differential amplifier as latch stage has been used in proposed comparator. The simulation result of ADC is operating at 5GHz sampling frequency and its delay and power dissipation is 419.9ns and 15.2 mw respectively. At 5GHz the average power dissipation of the encoder circuit is 58.5uw and delay 1.29 ns and proposed comparator delay is 1.1ns.
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