The World Wide Web is a huge, growing repository of information on a wide range of topics. It is ... more The World Wide Web is a huge, growing repository of information on a wide range of topics. It is also becoming important, commercially and sociologically, as a place of human interaction within different communities. In this paper we present an experimental study of the structure of the Web. We analyze link topologies of various communities, and patterns of mirroring of
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03, 2003
FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edi... more FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardwareassisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any FPGA and how they can be implemented on top of LUT networks in cases where modification of the FPGA itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an FPGA implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02, 2002
The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream lin... more The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware.
Recongurable computing devices oer substantial improvements in functional density and yield ver- ... more Recongurable computing devices oer substantial improvements in functional density and yield ver- sus traditional microprocessors, yet remain out of general-purpose use due in part to their diculty of programming and lack of cross-device compati- bility. This project presents a recongurable archi- tecture which supports automated compilation and cross-device compatibility by virtualizing hardware resources and automating management thereof in op- erating
The World Wide Web is a huge, growing repository of information on a wide range of topics. It is ... more The World Wide Web is a huge, growing repository of information on a wide range of topics. It is also becoming important, commercially and sociologically, as a place of human interaction within different communities. In this paper we present an experimental study of the structure of the Web. We analyze link topologies of various communities, and patterns of mirroring of
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03, 2003
FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edi... more FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardwareassisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any FPGA and how they can be implemented on top of LUT networks in cases where modification of the FPGA itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an FPGA implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02, 2002
The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream lin... more The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware.
Recongurable computing devices oer substantial improvements in functional density and yield ver- ... more Recongurable computing devices oer substantial improvements in functional density and yield ver- sus traditional microprocessors, yet remain out of general-purpose use due in part to their diculty of programming and lack of cross-device compati- bility. This project presents a recongurable archi- tecture which supports automated compilation and cross-device compatibility by virtualizing hardware resources and automating management thereof in op- erating
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Papers by Randy Huang