Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This ... more Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Robotics is the new-age domain of technology that deals with bringing a collaboration of all disc... more Robotics is the new-age domain of technology that deals with bringing a collaboration of all disciplines of sciences and engineering to create a mechanical machine that may or may not work entirely independently but definitely focuses on making human lives much easier. It has repeatedly shown its ability to change lives at home and in the industry. As the field of robotics research grows and reaches new worlds, the military is one area where advances can have a significant impact, and the government is aware of this. Military technology has come a long way from the days where soldiers had to walk into traps, putting their own lives in danger for their fellow soldiers, to today, when soldiers have robots walk into the same traps with possibility and result of zero human casualties. High-risk military operations such as mine detection, bomb defusing, fighter pilot aviation, and entering enemy territory without complete knowledge of what is to come are all tasks that can be programmed in a way that makes them accustomed to scenarios like these, either by intensive machine learning algorithms or artificially intelligent robot systems. Military soldiers are human capital; they are not self-driving robots; they are living beings with emotions, fears, and weaknesses, and they will almost always be unreliable as compared to computers and robots. They are easily affected by environmental effects and are vulnerable to external influences. The government's costs for deployed troops, such as training and salaries, are extremely high. As a result, the solution is to build AI robots for defence operations that can sense, collect data by observing surroundings as any human soldier would, and report it back to a workstation where it can be used for strategy building and planning on what the next step should be during a mission, thus making the army better prepared for any kind of trouble that might be on their way. In this paper, the survey and bibliometric analysis of AIbased IoT managed Swarm Robots from the Scopus repository is discussed, which analyses research by area, notable authors, organizations, funding agencies and countries. Statistical analysis of literature published as journals, articles and papers that aids in understanding the global influence of publication is called Bibliometric analysis. This paper is a thorough analysis of 84 research papers as obtained from the Scopus repository on the 3rd of April 2021. GPS Visualizer, Gephi, wordcloud, and ScienceScape are open source softwares used in the visualization review. As previously mentioned, the visualization assists in a quick and easy interpretation of the different viewpoints in a particular study domain pursuit.
Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning al... more Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources along with customized logic blocks, makes FPGA a perfect candidate for CNN model. Also, the major advantage of FPGA in the case of CNN is its parallelism and pipelining architecture which helps to accelerate CNN operations. The primary goal of this bibliometric review is to det...
Atualmente o mundo corporativo exige conhecimentos, habilidades e atitudes dos seus gestores, ale... more Atualmente o mundo corporativo exige conhecimentos, habilidades e atitudes dos seus gestores, alem dos conhecimentos tecnicos necessarios no passado. A area de Treinamento e Desenvolvimento das organizacoes necessita buscar, cada dia mais, tecnicas de desenvolvimento de executivos, de forma a desenvolve-los para atender as exigencias de suas funcoes, desenvolvendo competencias e motivacoes diferenciadas, e prepara-los para tomada de decisoes e ter uma visao sistemica da organizacao. Muitas empresas utilizam os jogos de empresas com este objetivo. Este estudo objetiva verificar a aplicabilidade dos conceitos e habilidades adquiridas durante um jogo de empresas no cotidiano dos executivos, bem como na gestao de suas equipes, apos um periodo de dois a quatros anos da aplicacao. Atraves de pesquisa por meio de um levantamento de opiniao com executivos de uma multinacional da regiao sul-fluminense do estado Rio de Janeiro que participaram de jogos de empresa durante um Programa de Desenv...
International Journal of Advanced Trends in Computer Science and Engineering, 2020
Network on chip (NoC) has been recommended as an emerging alternative for scalability and perform... more Network on chip (NoC) has been recommended as an emerging alternative for scalability and performance needs of next generation System on chips (SoCs). NoCs are actually forecast to solve the bus based interconnection problem of SoC where large numbers of Intellectual property modules (IPs) are incorporated on a single chip for much better results. NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC. The architecture of router consists of an input port with buffers, arbiter, crossbar as well as an output port.The input block of NoC router requires buffers to keep the new data packets. These buffers improve the overall performance of the router in terms of throughput however they consume far more area and power. Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets. Therefore use of small buffer will help to optimize latency and area in the router design. One more issue of router design is scheduler which allows contention free transfer of data packets among several IP modules or perhaps processors. For starvation free scheduling, Iterative Serial in Line Protocol (iSLIP) scheduler with programmable priority encoder provides best solution. The proposed design of high performance single node router with small side buffer in the input block and iSLIP scheduler has been implemented on FPGA in this paper.
International journal of engineering and technology, Apr 3, 2018
Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip... more Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip (SoC). The NoC provides a solution to the communication bottleneck of the bus based interconnection in SoC, where large numbers of Intellectual modules are integrated on a single chip for better performance. In NoC architecture, the router is a dominant component, which should provide contention free architecture with low latency. The router consists of input block, scheduler and crossbar switch. The design of scheduler leads the performance of the NoC router in terms of latency. Hence the starvation free scheduler is paramount importantin the NoC router design. iSLIP (Iterative serial line internet protocol) scheduler has programmable priority encoder which makes it fast and efficient scheduler over round robin arbiter. In this paper 2x4 NoC router using iSLIPscheduler is proposed. The proposed design is implemented using the Verilog programming on Xilinx Spartan 3 device.
Embedded Control System for Flash Lamp Pumped Solid-State Nd:Glass LASER Power Supply
High-power solid state Nd:glass lasers find applications in diverse fields of industry and techno... more High-power solid state Nd:glass lasers find applications in diverse fields of industry and technology[1]. These lasers are pumped by flash lamps of different sizes. Flash lamps are intense source of wideband light ranging from infrared to ultraviolet. Nd: glass absorption band lies within the emission band of Xenon flash lamps[2]. This paper reports the development of a closed loop standalone embedded control system and the Graphical User Interface (GUI) for flash lamp power supply. The GUI is developed using the Processing software, which is an open-source Java-based software. The microcontroller-based control system continuously monitors and controls the charging process of the energy storage capacitor banks. After the user defined energy is stored on the capacitor banks, the control system generates trigger signals to couple the stored energy to flash lamp load and thereby convert the electrical energy into intense light pulse for pumping of the laser medium. The control system i...
International Journal of Advanced Trends in Computer Science and Engineering, 2020
Network on chip (NoC) has been recommended as an emerging alternative for scalability and perform... more Network on chip (NoC) has been recommended as an emerging alternative for scalability and performance needs of next generation System on chips (SoCs). NoCs are actually forecast to solve the bus based interconnection problem of SoC where large numbers of Intellectual property modules (IPs) are incorporated on a single chip for much better results. NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC. The architecture of router consists of an input port with buffers, arbiter, crossbar as well as an output port.The input block of NoC router requires buffers to keep the new data packets. These buffers improve the overall performance of the router in terms of throughput however they consume far more area and power. Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets. Therefore use of small buffer will help to optimize latency and area in the router design. One more issue of router design is scheduler which allows contention free transfer of data packets among several IP modules or perhaps processors. For starvation free scheduling, Iterative Serial in Line Protocol (iSLIP) scheduler with programmable priority encoder provides best solution. The proposed design of high performance single node router with small side buffer in the input block and iSLIP scheduler has been implemented on FPGA in this paper.
International Journal of Engineering and Technology, 2016
The traditional system on chip designs employ the shared bus architecture for data transfer in hi... more The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets. Keywords-MPSoC, NoC, Router, Minimally buffered deflection router (MinBD),FPGA I. INTRODUCTION As technology scaling allows the integration of billions of transistors on a chip, it evolves MPSoC architectures which allow more processors and more cores to be placed on a single chip. Usually for MPSoC architectures, interconnections among various devices or cores are based on shared bus. Share bus architecture allows only one communication transaction at a time. Hence scalability is a major concern with shared bus system. A solution for such communication bottleneck is use of switching network, NoC(Network on chip) to interconnect various cores of MPSoC [2]. NoC has emerged as scalable and suitable design approach to solve the interconnection problem for MPSoC architecture. NoC architecture consists of three main parts, namely routers, link and network interface through which cores are interconnected to the NoC. Router is the heart of NoC as it coordinates data packet propagation from source to destination port based on information received from scheduler. Router consists of input port, arbiter, crossbar and output port. In most of the router design, input port is having buffer to temporarily store data packets and then transfer to destination port through crossbar. These buffers improve performance in term of increasing the bandwidth efficiency but consume significant power. These buffers consume dynamic power when read/ write operation is taking place and static energy when they are empty. Secondly buffers occupy more chip network area. In the TRIPS prototype chip, input buffers of routers were occupying 75% of total on chip network area. Hence there is a need for bufferless routers which eliminate input and output buffers [3]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7]. Yu Cai et al. Prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or tours topology compared with buffered architecture [9]. CHIPPER NoC implementation shows that when compare with buffered routing, it reduces average network power by 54% and area by 36.2% for 8X8 mesh topology [5]. The key idea for bufferless routing is that data packets are never buffered in the network. When two packets contend for the same link, one is deflected. Thus Bufferless deflection routing causes unnecessary hopping of data packets for high network utilization. It increases data packets traversals and reduces network throughput and also increases dynamic power. MinBD (minimally buffered deflection routing) provides the solution for bufferless deflection routing [4]. This paper is organized as follows. In section II, we discussed working principle of MinBD deflection router. Implementation of efficient input block of router is presented in section III. In section IV, we evaluate our proposed design for various test cases. Router input block is implemented on FPGA. The conclusions are given in section V.
International Journal of Engineering and Technology, 2016
The traditional system on chip designs employ the shared bus architecture for data transfer in hi... more The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets. Keywords-MPSoC, NoC, Router, Minimally buffered deflection router (MinBD),FPGA I. INTRODUCTION As technology scaling allows the integration of billions of transistors on a chip, it evolves MPSoC architectures which allow more processors and more cores to be placed on a single chip. Usually for MPSoC architectures, interconnections among various devices or cores are based on shared bus. Share bus architecture allows only one communication transaction at a time. Hence scalability is a major concern with shared bus system. A solution for such communication bottleneck is use of switching network, NoC(Network on chip) to interconnect various cores of MPSoC [2]. NoC has emerged as scalable and suitable design approach to solve the interconnection problem for MPSoC architecture. NoC architecture consists of three main parts, namely routers, link and network interface through which cores are interconnected to the NoC. Router is the heart of NoC as it coordinates data packet propagation from source to destination port based on information received from scheduler. Router consists of input port, arbiter, crossbar and output port. In most of the router design, input port is having buffer to temporarily store data packets and then transfer to destination port through crossbar. These buffers improve performance in term of increasing the bandwidth efficiency but consume significant power. These buffers consume dynamic power when read/ write operation is taking place and static energy when they are empty. Secondly buffers occupy more chip network area. In the TRIPS prototype chip, input buffers of routers were occupying 75% of total on chip network area. Hence there is a need for bufferless routers which eliminate input and output buffers [3]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7]. Yu Cai et al. Prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or tours topology compared with buffered architecture [9]. CHIPPER NoC implementation shows that when compare with buffered routing, it reduces average network power by 54% and area by 36.2% for 8X8 mesh topology [5]. The key idea for bufferless routing is that data packets are never buffered in the network. When two packets contend for the same link, one is deflected. Thus Bufferless deflection routing causes unnecessary hopping of data packets for high network utilization. It increases data packets traversals and reduces network throughput and also increases dynamic power. MinBD (minimally buffered deflection routing) provides the solution for bufferless deflection routing [4]. This paper is organized as follows. In section II, we discussed working principle of MinBD deflection router. Implementation of efficient input block of router is presented in section III. In section IV, we evaluate our proposed design for various test cases. Router input block is implemented on FPGA. The conclusions are given in section V.
Microcontroller Based Flow Control System for Canal Gates in Irrigation Canal Automation
2016 IEEE 6th International Conference on Advanced Computing (IACC), 2016
Modern growth in electronics systems, communication system, and information technology assist in ... more Modern growth in electronics systems, communication system, and information technology assist in designing canal automation system. The Canal irrigation is tremendously use source of water in irrigation. Microcontroller based system is very flexible for any modification required at site, while this system is cheaper than PLC can interface different modules easily. System involves intelligent Microcontroller based Remote Terminal Unit (RTU) which can communicate different sensors, communication modems, memory, ADC and different modules. In this paper we propose a microcontroller based design for flow control system for gate in canal automation. Flow control system consists of sub systems: RTU, Solar Power system, level measurement system, flow measurement system, gate actuator system, and communication system. In this paper more focus on flow control activities of Distributary, laterals and Direct Pipe Outlets (DPOs). Remote Terminal Unit monitors upstream level, downstream level, downstream flow, power status, gate opening, gate health and security. All system components designed to operates on solar power and battery backup. Conventional operational system has some drawbacks and inaccuracies. Proposed system helps to improve irrigation operational efficiency, power use, accuracy in measurement, water distribution and reactions to imbalance and controls the flow at gate location continuously. This system also helps to reduce water wastage and labour dependency.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This ... more Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Robotics is the new-age domain of technology that deals with bringing a collaboration of all disc... more Robotics is the new-age domain of technology that deals with bringing a collaboration of all disciplines of sciences and engineering to create a mechanical machine that may or may not work entirely independently but definitely focuses on making human lives much easier. It has repeatedly shown its ability to change lives at home and in the industry. As the field of robotics research grows and reaches new worlds, the military is one area where advances can have a significant impact, and the government is aware of this. Military technology has come a long way from the days where soldiers had to walk into traps, putting their own lives in danger for their fellow soldiers, to today, when soldiers have robots walk into the same traps with possibility and result of zero human casualties. High-risk military operations such as mine detection, bomb defusing, fighter pilot aviation, and entering enemy territory without complete knowledge of what is to come are all tasks that can be programmed in a way that makes them accustomed to scenarios like these, either by intensive machine learning algorithms or artificially intelligent robot systems. Military soldiers are human capital; they are not self-driving robots; they are living beings with emotions, fears, and weaknesses, and they will almost always be unreliable as compared to computers and robots. They are easily affected by environmental effects and are vulnerable to external influences. The government's costs for deployed troops, such as training and salaries, are extremely high. As a result, the solution is to build AI robots for defence operations that can sense, collect data by observing surroundings as any human soldier would, and report it back to a workstation where it can be used for strategy building and planning on what the next step should be during a mission, thus making the army better prepared for any kind of trouble that might be on their way. In this paper, the survey and bibliometric analysis of AIbased IoT managed Swarm Robots from the Scopus repository is discussed, which analyses research by area, notable authors, organizations, funding agencies and countries. Statistical analysis of literature published as journals, articles and papers that aids in understanding the global influence of publication is called Bibliometric analysis. This paper is a thorough analysis of 84 research papers as obtained from the Scopus repository on the 3rd of April 2021. GPS Visualizer, Gephi, wordcloud, and ScienceScape are open source softwares used in the visualization review. As previously mentioned, the visualization assists in a quick and easy interpretation of the different viewpoints in a particular study domain pursuit.
Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning al... more Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources along with customized logic blocks, makes FPGA a perfect candidate for CNN model. Also, the major advantage of FPGA in the case of CNN is its parallelism and pipelining architecture which helps to accelerate CNN operations. The primary goal of this bibliometric review is to det...
Atualmente o mundo corporativo exige conhecimentos, habilidades e atitudes dos seus gestores, ale... more Atualmente o mundo corporativo exige conhecimentos, habilidades e atitudes dos seus gestores, alem dos conhecimentos tecnicos necessarios no passado. A area de Treinamento e Desenvolvimento das organizacoes necessita buscar, cada dia mais, tecnicas de desenvolvimento de executivos, de forma a desenvolve-los para atender as exigencias de suas funcoes, desenvolvendo competencias e motivacoes diferenciadas, e prepara-los para tomada de decisoes e ter uma visao sistemica da organizacao. Muitas empresas utilizam os jogos de empresas com este objetivo. Este estudo objetiva verificar a aplicabilidade dos conceitos e habilidades adquiridas durante um jogo de empresas no cotidiano dos executivos, bem como na gestao de suas equipes, apos um periodo de dois a quatros anos da aplicacao. Atraves de pesquisa por meio de um levantamento de opiniao com executivos de uma multinacional da regiao sul-fluminense do estado Rio de Janeiro que participaram de jogos de empresa durante um Programa de Desenv...
International Journal of Advanced Trends in Computer Science and Engineering, 2020
Network on chip (NoC) has been recommended as an emerging alternative for scalability and perform... more Network on chip (NoC) has been recommended as an emerging alternative for scalability and performance needs of next generation System on chips (SoCs). NoCs are actually forecast to solve the bus based interconnection problem of SoC where large numbers of Intellectual property modules (IPs) are incorporated on a single chip for much better results. NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC. The architecture of router consists of an input port with buffers, arbiter, crossbar as well as an output port.The input block of NoC router requires buffers to keep the new data packets. These buffers improve the overall performance of the router in terms of throughput however they consume far more area and power. Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets. Therefore use of small buffer will help to optimize latency and area in the router design. One more issue of router design is scheduler which allows contention free transfer of data packets among several IP modules or perhaps processors. For starvation free scheduling, Iterative Serial in Line Protocol (iSLIP) scheduler with programmable priority encoder provides best solution. The proposed design of high performance single node router with small side buffer in the input block and iSLIP scheduler has been implemented on FPGA in this paper.
International journal of engineering and technology, Apr 3, 2018
Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip... more Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip (SoC). The NoC provides a solution to the communication bottleneck of the bus based interconnection in SoC, where large numbers of Intellectual modules are integrated on a single chip for better performance. In NoC architecture, the router is a dominant component, which should provide contention free architecture with low latency. The router consists of input block, scheduler and crossbar switch. The design of scheduler leads the performance of the NoC router in terms of latency. Hence the starvation free scheduler is paramount importantin the NoC router design. iSLIP (Iterative serial line internet protocol) scheduler has programmable priority encoder which makes it fast and efficient scheduler over round robin arbiter. In this paper 2x4 NoC router using iSLIPscheduler is proposed. The proposed design is implemented using the Verilog programming on Xilinx Spartan 3 device.
Embedded Control System for Flash Lamp Pumped Solid-State Nd:Glass LASER Power Supply
High-power solid state Nd:glass lasers find applications in diverse fields of industry and techno... more High-power solid state Nd:glass lasers find applications in diverse fields of industry and technology[1]. These lasers are pumped by flash lamps of different sizes. Flash lamps are intense source of wideband light ranging from infrared to ultraviolet. Nd: glass absorption band lies within the emission band of Xenon flash lamps[2]. This paper reports the development of a closed loop standalone embedded control system and the Graphical User Interface (GUI) for flash lamp power supply. The GUI is developed using the Processing software, which is an open-source Java-based software. The microcontroller-based control system continuously monitors and controls the charging process of the energy storage capacitor banks. After the user defined energy is stored on the capacitor banks, the control system generates trigger signals to couple the stored energy to flash lamp load and thereby convert the electrical energy into intense light pulse for pumping of the laser medium. The control system i...
International Journal of Advanced Trends in Computer Science and Engineering, 2020
Network on chip (NoC) has been recommended as an emerging alternative for scalability and perform... more Network on chip (NoC) has been recommended as an emerging alternative for scalability and performance needs of next generation System on chips (SoCs). NoCs are actually forecast to solve the bus based interconnection problem of SoC where large numbers of Intellectual property modules (IPs) are incorporated on a single chip for much better results. NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC. The architecture of router consists of an input port with buffers, arbiter, crossbar as well as an output port.The input block of NoC router requires buffers to keep the new data packets. These buffers improve the overall performance of the router in terms of throughput however they consume far more area and power. Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets. Therefore use of small buffer will help to optimize latency and area in the router design. One more issue of router design is scheduler which allows contention free transfer of data packets among several IP modules or perhaps processors. For starvation free scheduling, Iterative Serial in Line Protocol (iSLIP) scheduler with programmable priority encoder provides best solution. The proposed design of high performance single node router with small side buffer in the input block and iSLIP scheduler has been implemented on FPGA in this paper.
International Journal of Engineering and Technology, 2016
The traditional system on chip designs employ the shared bus architecture for data transfer in hi... more The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets. Keywords-MPSoC, NoC, Router, Minimally buffered deflection router (MinBD),FPGA I. INTRODUCTION As technology scaling allows the integration of billions of transistors on a chip, it evolves MPSoC architectures which allow more processors and more cores to be placed on a single chip. Usually for MPSoC architectures, interconnections among various devices or cores are based on shared bus. Share bus architecture allows only one communication transaction at a time. Hence scalability is a major concern with shared bus system. A solution for such communication bottleneck is use of switching network, NoC(Network on chip) to interconnect various cores of MPSoC [2]. NoC has emerged as scalable and suitable design approach to solve the interconnection problem for MPSoC architecture. NoC architecture consists of three main parts, namely routers, link and network interface through which cores are interconnected to the NoC. Router is the heart of NoC as it coordinates data packet propagation from source to destination port based on information received from scheduler. Router consists of input port, arbiter, crossbar and output port. In most of the router design, input port is having buffer to temporarily store data packets and then transfer to destination port through crossbar. These buffers improve performance in term of increasing the bandwidth efficiency but consume significant power. These buffers consume dynamic power when read/ write operation is taking place and static energy when they are empty. Secondly buffers occupy more chip network area. In the TRIPS prototype chip, input buffers of routers were occupying 75% of total on chip network area. Hence there is a need for bufferless routers which eliminate input and output buffers [3]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7]. Yu Cai et al. Prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or tours topology compared with buffered architecture [9]. CHIPPER NoC implementation shows that when compare with buffered routing, it reduces average network power by 54% and area by 36.2% for 8X8 mesh topology [5]. The key idea for bufferless routing is that data packets are never buffered in the network. When two packets contend for the same link, one is deflected. Thus Bufferless deflection routing causes unnecessary hopping of data packets for high network utilization. It increases data packets traversals and reduces network throughput and also increases dynamic power. MinBD (minimally buffered deflection routing) provides the solution for bufferless deflection routing [4]. This paper is organized as follows. In section II, we discussed working principle of MinBD deflection router. Implementation of efficient input block of router is presented in section III. In section IV, we evaluate our proposed design for various test cases. Router input block is implemented on FPGA. The conclusions are given in section V.
International Journal of Engineering and Technology, 2016
The traditional system on chip designs employ the shared bus architecture for data transfer in hi... more The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets. Keywords-MPSoC, NoC, Router, Minimally buffered deflection router (MinBD),FPGA I. INTRODUCTION As technology scaling allows the integration of billions of transistors on a chip, it evolves MPSoC architectures which allow more processors and more cores to be placed on a single chip. Usually for MPSoC architectures, interconnections among various devices or cores are based on shared bus. Share bus architecture allows only one communication transaction at a time. Hence scalability is a major concern with shared bus system. A solution for such communication bottleneck is use of switching network, NoC(Network on chip) to interconnect various cores of MPSoC [2]. NoC has emerged as scalable and suitable design approach to solve the interconnection problem for MPSoC architecture. NoC architecture consists of three main parts, namely routers, link and network interface through which cores are interconnected to the NoC. Router is the heart of NoC as it coordinates data packet propagation from source to destination port based on information received from scheduler. Router consists of input port, arbiter, crossbar and output port. In most of the router design, input port is having buffer to temporarily store data packets and then transfer to destination port through crossbar. These buffers improve performance in term of increasing the bandwidth efficiency but consume significant power. These buffers consume dynamic power when read/ write operation is taking place and static energy when they are empty. Secondly buffers occupy more chip network area. In the TRIPS prototype chip, input buffers of routers were occupying 75% of total on chip network area. Hence there is a need for bufferless routers which eliminate input and output buffers [3]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7]. Yu Cai et al. Prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or tours topology compared with buffered architecture [9]. CHIPPER NoC implementation shows that when compare with buffered routing, it reduces average network power by 54% and area by 36.2% for 8X8 mesh topology [5]. The key idea for bufferless routing is that data packets are never buffered in the network. When two packets contend for the same link, one is deflected. Thus Bufferless deflection routing causes unnecessary hopping of data packets for high network utilization. It increases data packets traversals and reduces network throughput and also increases dynamic power. MinBD (minimally buffered deflection routing) provides the solution for bufferless deflection routing [4]. This paper is organized as follows. In section II, we discussed working principle of MinBD deflection router. Implementation of efficient input block of router is presented in section III. In section IV, we evaluate our proposed design for various test cases. Router input block is implemented on FPGA. The conclusions are given in section V.
Microcontroller Based Flow Control System for Canal Gates in Irrigation Canal Automation
2016 IEEE 6th International Conference on Advanced Computing (IACC), 2016
Modern growth in electronics systems, communication system, and information technology assist in ... more Modern growth in electronics systems, communication system, and information technology assist in designing canal automation system. The Canal irrigation is tremendously use source of water in irrigation. Microcontroller based system is very flexible for any modification required at site, while this system is cheaper than PLC can interface different modules easily. System involves intelligent Microcontroller based Remote Terminal Unit (RTU) which can communicate different sensors, communication modems, memory, ADC and different modules. In this paper we propose a microcontroller based design for flow control system for gate in canal automation. Flow control system consists of sub systems: RTU, Solar Power system, level measurement system, flow measurement system, gate actuator system, and communication system. In this paper more focus on flow control activities of Distributary, laterals and Direct Pipe Outlets (DPOs). Remote Terminal Unit monitors upstream level, downstream level, downstream flow, power status, gate opening, gate health and security. All system components designed to operates on solar power and battery backup. Conventional operational system has some drawbacks and inaccuracies. Proposed system helps to improve irrigation operational efficiency, power use, accuracy in measurement, water distribution and reactions to imbalance and controls the flow at gate location continuously. This system also helps to reduce water wastage and labour dependency.
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