Papers by Pietro Nannipieri
Electronics
Random number generators are a key element for various applications, such as computer simulation,... more Random number generators are a key element for various applications, such as computer simulation, statistical sampling, and cryptography. They are used to generate/derive cryptographic keys and non-repeating values, e.g., for symmetric or public key cyphers. The strength of a data protection system against cyber attacks corresponds to the strength of the weakest point in the security chain. Therefore, from a mathematical point of view, the security chain can be compromised even if the strongest algorithm is implemented. In fact, if the system requires keys or other random values and the generation process shows a certain vulnerability, the security of the system itself can be compromised. In this article, we present the most reliable tools and methodologies and the main standardisation efforts in the field of computer security to assess the quality of random number generators and ensure that they can be applied to computer security applications by offering adequate security strength...
Electronics
Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems... more Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than 50% of the total project time. Several solutions have been developed with the goal of automating this task, integrating various steps of the Very Large Scale Integration design flow, but without addressing the exploration of the design space on both the software and hardware sides. Early in the co-design phase, designers break down the system into hardware and software parts taking into account different choices to explore the design space. This work describes the use of a framework for automating the verification of such choices, considering both hardware and software development flows. The framework automates compilation of software, cyc...
ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components
2022 IEEE Aerospace Conference (AERO), Mar 5, 2022
Satellite Serial High-Speed On-Board Communication: Design of a SpaceFibre-Based Ecosystem for Next Generation Satellite Data-Handling
Negli ultimi anni, la banda richiesta per la gestione dei dati a bordo dei satelliti è cresciuta ... more Negli ultimi anni, la banda richiesta per la gestione dei dati a bordo dei satelliti è cresciuta in maniera significativa. Le soluzioni presenti nello stato dell’arte, come SpaceWire, sono al momento non adeguate a soddisfare i requisiti di tutte le missioni future. Questo ha portato alla nascita di una serie di diversi protocolli di comunicazioni ad alta velocità, ciascuno con le sue caratteristiche, i suoi vantaggi, i suoi svantaggi, in modo da poter soddisfare i requisiti dei nuovi satelliti. L’agenzia spaziale Europea ha promosso attivamente lo sviluppo di un protocollo aperto (liberamente accessibile): SpaceFibre, il cui standard è stato pubblicato dall’ECSS nel maggio 2019, dopo un complesso percorso di revisione. Il protocollo SpaceFibre è in grado di sostenere velocità di comunicazione fino a 6,25 Gbps per linea dati, con fino a 16 linee che possono operare in parallelo. Offre una avanzata Quality of Service e la possibilità di individuare, isolare e recuperare da errori (Fa...
Exploiting LabViewFpga Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards
2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
PXI FPGA Peripheral Modules by National Instruments are meant to be used in LabView even without ... more PXI FPGA Peripheral Modules by National Instruments are meant to be used in LabView even without any previous knowledge of Hardware Description Languages (HDL) and let users to hardware-accelerate their own test and measurement setups. However, designers fluent in HDL languages avoid such closed technology targets due to impossibility to include third-party designs or the needed over-effort to implement large and complex architectures into it, such as soft-core based systems. In this paper a partially automated workflow to benefit of the PXI environment allowing advanced HDL engineers to implement complex architectures is presented with reference to two successful use-case examples.
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators
2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes
Lecture Notes in Electrical Engineering
A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2018
In the last few years, data rate requirement on on-board satellite communication systems signific... more In the last few years, data rate requirement on on-board satellite communication systems significantly grown. The need of high speed networks led to the birth of the SpaceFibre protocol, which is able to run at several Gigabit per second and operates over both optical fibre and copper cables. A key feature of SpaceFibre is the possibility to have multi lane link, which increases the overall achievable data rate and link reliability. The growing complexity of satellite payload communication systems requires the definition an accurate monitoring and testing system. In this paper a multi lane SpaceFibre interface integrated in a System on a Chip is presented as enabling technology for an electrical ground segment equipment.
The SpaceFibre Standard
Next-Generation High-Speed Satellite Interconnect, 2021
In this chapter we will introduce the SpaceFibre standard, providing an overview of its layers. T... more In this chapter we will introduce the SpaceFibre standard, providing an overview of its layers. The objective of the chapter is to support the reader in the understanding of the different layers; even though the standard contains all the necessary information to build a SpaceFibre-based system, it can be difficult to be understood at first. We do not intend to substitute the standard, which remains the reference for the development of SpaceFibre-based products, but to provide a tool for a better and faster understanding of it.
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus
Lecture Notes in Electrical Engineering, 2020
Nowadays, requirements for satellite electronics are becoming more stringent due to the increasin... more Nowadays, requirements for satellite electronics are becoming more stringent due to the increasing complexity of space missions. In particular, data rate requirement is growing up due to the adoption of high-speed payloads such as Synthetic Aperture Radars and hyper-spectral imagers that overcome the capability of state-of-the-art on-board data handling system. The European Space Agency answered to this request introducing a new high-speed communication protocol, SpaceFibre. At the same time, data collected by high-speed interfaces may be processed on-board with specific hardware or general-purpose microprocessor such as the LEON3. The aim of this paper is to describe the integration of a SpaceFibre IP core in the Cohbam Gaisler GRLIB library, to integrate the functionalities offered by the SpaceFibre CODEC with the potential of the LEON3 microprocessor. Implementation results on a Xilinx Virtex-6 and an analysis of the performance of the SpaceFibre interface on an AMBA 2.0 AHB bus are presented.
As the number of earth observation missions increases, and so does the number of images acquired ... more As the number of earth observation missions increases, and so does the number of images acquired by satellites, the need of optimizing on-board mass-memory allocation and data transmitted to ground becomes more and more important, as both are limited resources. Currently, large players in the space industry are still designign Instrument Control Units which are largely customized so, once developed, they can only be exploited for the single mission they have been designed for. On the other hand, the unavailability of commercial flexible, programmable and space-qualified solutions ready to be integrated keeps small-medium enterprises out of this market, since mostly large-scale integrators have the resources needed to undertake custom development at unit level.<br> The Instrument Control Unit with Artificial Intelligence Engine System on Chip presented in this work aims at changing the rules of image/data handling and processing on-board satellites, overcoming the downsides of ...
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022
This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encr... more This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encryption standard (AES)-based block cipher modes, including the more advanced cipher-based MAC (CMAC), counter with CBC-MAC (CCM), Galois counter mode (GCM), and XOR-encrypt-XOR-based tweaked-codebook mode with ciphertext stealing (XTS) modes. The proposed design implements advanced and innovative features in HW, such as AES key secure management, on-chip clock randomization, and access privilege mechanisms. The system has been tested in a RISC-V-based system-on-chip (SoC), specifically designed for this purpose, on an Ultrascale + Xilinx FPGA, analyzing resource and power consumption, together with system performances. The cryptoprocessor has been then synthesized on a 7-nm CMOS standard-cells technology; performances, complexity, and power consumption information are analyzed and compared with the state of the art. The proposed cryptoprocessor is ready to be embedded within the innovative European Processor Initiative (EPI) chip.
Application of FBG sensors to temperature measurement on board of the REXUS 22 sounding rocket in the framework of the U-PHOS project
2017 IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace), 2017
U-PHOS (Upgraded PHP Only for Space) is a project developed within the REXUS/BEXUS programme fram... more U-PHOS (Upgraded PHP Only for Space) is a project developed within the REXUS/BEXUS programme framework, by a team of students from the University of Pisa with the goal to analyse and characterize the behaviour of a Pulsating Heat Pipe (PHP), one of the most attractive two phases passive systems for thermal management in space applications. The PHP consists of a sealed serpentine capillary tube filled with a working fluid. The heat is efficiently transported by means of the combined action of phase change and capillary forces, so no extra equipment is required. The project aims at investigating the thermal response of such a device under a milli-gravity condition, in order to assess its effectiveness in space conditions. To do so, the power delivered to the system, the internal pressure of the PHP and in particular its temperature in several points must be measured. The temperature measurements are performed by an innovative fibre sensing solution based on arrays of fibre Bragg Gratings (FBGs), which act as temperature sensors at specific locations along only one optical fibre. This paper intends to describe the system built by the students, focusing on the FBG temperature measurements systems. A comparison between the adopted solution and other possible measurement systems is performed, highlighting advantages and drawbacks.
Entropy, 2022
In the cybersecurity field, the generation of random numbers is extremely important because they ... more In the cybersecurity field, the generation of random numbers is extremely important because they are employed in different applications such as the generation/derivation of cryptographic keys, nonces, and initialization vectors. The more unpredictable the random sequence, the higher its quality and the lower the probability of recovering the value of those random numbers for an adversary. Cryptographically Secure Pseudo-Random Number Generators (CSPRNGs) are random number generators (RNGs) with specific properties and whose output sequence has such a degree of randomness that it cannot be distinguished from an ideal random sequence. In this work, we designed an all-digital RNG, which includes a Deterministic Random Bit Generator (DRBG) that meets the security requirements for cryptographic applications as CSPRNG, plus an entropy source that showed high portability and a high level of entropy. The proposed design has been intensively tested against both NIST and BSI suites to assess ...
Next-Generation High-Speed Satellite Interconnect, 2021
The use of general descriptive names, registered names, trademarks, service marks, etc. in this p... more The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.
Design of a SpaceWire/SpaceFibre EGSE system based on PXI industry standard
2019 IEEE 5th International Workshop on Metrology for AeroSpace (MetroAeroSpace), 2019
This paper introduces a comprehensive test equipment for early adopters of the new ECSS satellite... more This paper introduces a comprehensive test equipment for early adopters of the new ECSS satellite on-board serial high-speed communication protocol, SpaceFibre, maintaining also retro-compatibility with its precursor, SpaceWire. The presented system is based on the PCI eXtension for Instrumentation (PXI) industry standard and designed with cutting edge high level synthesis techniques. It offers support in development of both SpaceWire and SpaceFibre devices, even in cross standard communication, for current and future generation spacecraft missions. Thanks to its native integration in the PXI platform, the proposed Electrical Ground Segment Equipment (EGSE) system is ready to be integrated out of the box in larger prior existing testing and simulation environment.
Upgraded Pulsating Heat Pipe Only For Space (U-Phos): Results of the 22nd Rexus Sounding Rocket Campaign
A large tube may still behave, to a certain extent, as a capillary in a micro-gravity environment... more A large tube may still behave, to a certain extent, as a capillary in a micro-gravity environment. This very basic concept is here applied to a two-phase passive heat transfer devices in order to obtain a new family of hybrid wickless heat pipes. Indeed, a Loop Thermosyphon, which usually consists of a large tube, closed end to end in a loop, evacuated and partially filled with a working fluid and intrinsically gravity assisted, may become a capillary tube in space condition and turn its thermo-fluidic behavior into a so called Pulsating Heat Pipe (PHP), or better, a Space Pulsating Heat Pipe (SPHP). Since the objective of the present work is to experimentally demonstrate the feasibility of such a hybrid device, a SPHP has been designed, built, instrumented and tested both on ground and microgravity conditions on the 22 ESA REXUS Sounding Rocket Campaign. Ground tests demonstrate that the device effectively work as a gravity assisted loop thermosyphon, whether the sounding rocket da...
Energies, 2021
Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low l... more Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified versi...
SpaceART SpaceWire and SpaceFibre Analyser Real-Time
2020 IEEE 7th International Workshop on Metrology for AeroSpace (MetroAeroSpace), 2020
Spacecrafts and space missions require in-depth testing during verification and integration phase... more Spacecrafts and space missions require in-depth testing during verification and integration phases. These are accomplished through very specific test equipment that effectively allow investigating any test scenario for which the satellite has been designed. All test equipment and tools designed for this scope represent the Electric Ground Segment Equipment of a mission. In this paper complete test equipment for the most widespread On-Board Data Handling protocols is presented: the SpaceWire/SpaceFibre Analyser Real-Time (SpaceART). SpaceART provides serial link communication interfaces for present and future spacecraft On-Board Data Handling: the State- Of-The-Art SpaceWire technology, the non-standardized solution usually adopted for Gigabit communication WizardLink and the newly released standard SpaceFibre protocol. SpaceART is an innovative instrument easy to customize upon user requirements, regardless of the peculiarity of desired test scenarios. After a brief introduction to the currently available SpaceFibre compliant test-equipment, the paper provides an overview of SpaceART architecture. Finally, two of the most relevant real use cases are reported as proof of the instrument’s effectiveness.
2017 IEEE Global Engineering Education Conference (EDUCON), 2017
U-PHOS (Upgraded PHP Only for Space) is a project developed by a team of students from the Univer... more U-PHOS (Upgraded PHP Only for Space) is a project developed by a team of students from the University of Pisa with the goal to analyze and characterize the behavior of a Pulsating Heat Pipe (PHP), one of the most attractive two phases passive systems for thermal management in space applications. The PHP consists of a sealed serpentine capillary tube filled with a working fluid. The heat is efficiently transported by means of the combined action of phase change and capillary forces, so no extra equipment is required. The project aims at investigating the thermal response of such a device under a milli-gravity condition, in order to assess its effectiveness in space conditions. U-PHOS is one of the selected experiment of the REXUS/BEXUS programme, which allows European university students to carry out scientific and technical experiments on research rockets and balloons, thanks to a bilateral agency agreement between the German Aerospace Centre (DLR) and the Swedish National Space Board (SNSB) in collaboration with ESA. 19 students from the University of Pisa, with different backgrounds, compose the U-PHOS team. Students had the chance to completely design, build and test the experiment, which will flight up to space in March 2017. This paper intends to describe the work done by the students, their organization and how this experience empowered their careers, from both an academic and professional point of view.
Uploads
Papers by Pietro Nannipieri