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Pete Sedcole

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Papers by Pete Sedcole

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Run-Time Integration of Reconfigurable Video Processing Systems

Arrays can be customised and adaptive if assembled from modular components at run-time. This pape... more Arrays can be customised and adaptive if assembled from modular components at run-time. This paper examines realising run-time system assembly by extension of platform-based design. Two major challenges are addressed in this paper. Firstly, the design of a reconfigurable platform architecture suitable for run-time system assembly is described. Different systems are constructed by integrating the platform architecture with different modular components, which employ the communication infrastructure supplied by the platform in order to interact. Secondly, where on-chip communications channels use shared media, we propose techniques for modelling the inter-module communication behaviour based on statistical time division multiplexing. The proposed techniques enable system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An indepth analysis is presented, and then verified with cycle-accurate simulations for...

Parametric yield in FPGAs due to within-die delay variations

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07, 2007

Variations in the semiconductor fabrication process results in variability in parameters between ... more Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The reconfigurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

On-Chip Communication in Run-Time Assembled Reconfigurable Systems

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2006

Embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled fr... more Embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. This paper describes techniques for modelling inter-module channel behaviour based on statistical time division multiplexing. Where modules communicate over shared media, the proposed techniques enable systematic development of on-chip communication infrastructure to support run-time instantiation of components. Our techniques also allow system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented, and then verified with cycle-accurate simulations for the Sonic-on-chip reconfigurable platform for real-time video applications.

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing

First International Symposium on Networks-on-Chip (NOCS'07), 2007

Dynamic routing can substantially enhance the quality of service for multiprocessor communication... more Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implementing dynamic routing on a network-on-chip (NoC) platform requires a design that provides highly efficient optimal path computation coupled with reduced area and power consumption. In this paper, we present a hybrid analog-digital routing network design that enables efficient dynamic routing on an NoC architecture. The digital part provides accurate real-time traffic estimation using a temporal cost evaluation and adaptation scheme. The analog network, which is distributed within the digital communication network, provides an efficient implementation for the optimal routing algorithm with extremely low power consumption. Our results demonstrate the effectiveness of the hybrid analog-digital design, with a significant improvement in latency over the static routing for random hot spot traffics.

Within-die delay variability in 90nm FPGAs and beyond

2006 IEEE International Conference on Field Programmable Technology, 2006

Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This p... more Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This paper describes accurate measurement techniques for characterising both systematic and stochastic delay variability in FPGAs. Results and analysis are presented from measurements made on a sample of 90nm devices, showing that delay per logic element varies stochastically by ±3.54% on average over the set. The delay also varies by up to 3.66% across a single die from correlated sources of variability. The results are extrapolated to determine the impact at future technology nodes. The predicted significant performance degradation that variability will cause demonstrates the importance of new circuit or system design techniques to cope with variations in future FPGAs.

On-FPGA Communication Architectures and Design Factors

2006 International Conference on Field Programmable Logic and Applications, 2006

The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with ... more The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. This survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

Wave-pipelined signaling for on-FPGA communication

2008 International Conference on Field-Programmable Technology, 2008

On-FPGA communication is becoming more problematic as the long interconnection performance is det... more On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA. The throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous link. Two circuit designs are

Fault tolerant methods for reliability in FPGAs

2008 International Conference on Field Programmable Logic and Applications, 2008

Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs... more Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.

Throughput maximization for wave-pipelined interconnects using cascaded buffers and transistor sizing

2009 IEEE International Symposium on Circuits and Systems, 2009

ABSTRACT

Compensating for variability in FPGAs by re-mapping and re-placement

2009 International Conference on Field Programmable Logic and Applications, 2009

... [3] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, Parameter varia... more

Implementation of Wave-Pipelined Interconnects in FPGAs

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008

Global interconnection and communication at high clock frequencies are becoming more problematic ... more Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.

Global interconnections in FPGAs

Proceedings of the tenth international workshop on System level interconnect prediction - SLIP '08, 2008

This paper presents a new model for global routings in FP-GAs. The irregular interconnections in ... more This paper presents a new model for global routings in FP-GAs. The irregular interconnections in FPGAs can be generalized as multiple buffered interconnect stages, of which the electrical waveform can be adequately approximated. Based on the model, expressions of delay and fundamental throughput of the interconnections have been derived and validated. They are shown in line with the SPICE and FPGA experimental results. Moreover, the model shows that interconnection throughput can be significantly increased using wave-pipelined signaling instead of the conventional delay-based synchronous approach, as has been demonstrated in our FPGA experiments. We conclude this paper by having a discussion about a strategy to further enhance the interconnect throughput.

Degradation in FPGAs

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10, 2010

Progress in VLSI technology is driven by increasing circuit density through process scaling, but ... more Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for

Combating process variation on FPGAS with a precise at-speed delay measurement method

2008 International Conference on Field Programmable Logic and Applications, 2008

The goal of this PhD project is to devise a way to combat the effect of process variation on prop... more The goal of this PhD project is to devise a way to combat the effect of process variation on propagation delays in modern FPGAs. Through our research, we have devised a novel measurement method that is capable of measuring the delays of components on FPGAs with picosecond timing resolution and fine spatial granularity. The method avoids the use of external

Modelling and compensating for clock skew variability in FPGAs

2008 International Conference on Field-Programmable Technology, 2008

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process par... more As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognisant of within-die performance variability. This paper examines the effect of process variability on the clock resources in FPGA devices. A model of variation in clock skew in FPGA clock networks is presented. Techniques for reducing the impact of variations on the performance of implemented designs are proposed and analysed, demonstrating that skew variation can be reduced by 70% or more through a combination of phase adjustment and clock rerouting. Measurements on a Virtex-5 FPGA validate the feasibility and benefits of the proposed compensation strategies.

Characterisation of FPGA Clock Variability

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process par... more As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic overdesign. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FP-GAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.

Self-characterization of Combinatorial Circuit Delays in FPGAs

2007 International Conference on Field-Programmable Technology, 2007

This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial ci... more This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of lps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-IT FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

A Structured System Methodology for FPGA Based System-on-A-Chip Design

Field-Programmable Custom Computing Machines, 2004

The ever increasing quantities of logic resources combined with heterogeneous integrated performa... more The ever increasing quantities of logic resources combined with heterogeneous integrated performance enhancing primitives in high-end FPGAs creates a design complexity challenge that requires new methodologies to address. We present a structured system based design methodology which aims to increase productivity and exploit reconfigurability in large scale FPGAs. The methodology is exemplified by sonic-on-a-chip, a video image processing system.

A Structured Methodology for System-on-an-FPGA Design

Field-Programmable Logic and Applications, 2004

Increasing logic resources coupled with a proliferation of integrated performance enhancing primi... more Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which requires new methodologies to overcome. This paper presents a structured system based design methodology, centred around the concept of architecture reuse, which aims to increase productivity and exploit the reconfigurability of high-end FPGAs. The methodology is exemplified by

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Field-Programmable Logic and Applications, 2003

The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low... more The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low-power, flexible and adaptable integrated image processing systems. An architecture for a system-on-a-chip solution is proposed, based on reconfigurable computing. The inherent system modularity and the communication infrastructure are targeted at enhancing design productivity and reuse. Power consumption is addressed by a combination of efficient streaming data transfer

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Run-Time Integration of Reconfigurable Video Processing Systems

Arrays can be customised and adaptive if assembled from modular components at run-time. This pape... more Arrays can be customised and adaptive if assembled from modular components at run-time. This paper examines realising run-time system assembly by extension of platform-based design. Two major challenges are addressed in this paper. Firstly, the design of a reconfigurable platform architecture suitable for run-time system assembly is described. Different systems are constructed by integrating the platform architecture with different modular components, which employ the communication infrastructure supplied by the platform in order to interact. Secondly, where on-chip communications channels use shared media, we propose techniques for modelling the inter-module communication behaviour based on statistical time division multiplexing. The proposed techniques enable system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An indepth analysis is presented, and then verified with cycle-accurate simulations for...

Parametric yield in FPGAs due to within-die delay variations

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07, 2007

Variations in the semiconductor fabrication process results in variability in parameters between ... more Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The reconfigurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

On-Chip Communication in Run-Time Assembled Reconfigurable Systems

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2006

Embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled fr... more Embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. This paper describes techniques for modelling inter-module channel behaviour based on statistical time division multiplexing. Where modules communicate over shared media, the proposed techniques enable systematic development of on-chip communication infrastructure to support run-time instantiation of components. Our techniques also allow system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented, and then verified with cycle-accurate simulations for the Sonic-on-chip reconfigurable platform for real-time video applications.

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing

First International Symposium on Networks-on-Chip (NOCS'07), 2007

Dynamic routing can substantially enhance the quality of service for multiprocessor communication... more Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implementing dynamic routing on a network-on-chip (NoC) platform requires a design that provides highly efficient optimal path computation coupled with reduced area and power consumption. In this paper, we present a hybrid analog-digital routing network design that enables efficient dynamic routing on an NoC architecture. The digital part provides accurate real-time traffic estimation using a temporal cost evaluation and adaptation scheme. The analog network, which is distributed within the digital communication network, provides an efficient implementation for the optimal routing algorithm with extremely low power consumption. Our results demonstrate the effectiveness of the hybrid analog-digital design, with a significant improvement in latency over the static routing for random hot spot traffics.

Within-die delay variability in 90nm FPGAs and beyond

2006 IEEE International Conference on Field Programmable Technology, 2006

Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This p... more Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This paper describes accurate measurement techniques for characterising both systematic and stochastic delay variability in FPGAs. Results and analysis are presented from measurements made on a sample of 90nm devices, showing that delay per logic element varies stochastically by ±3.54% on average over the set. The delay also varies by up to 3.66% across a single die from correlated sources of variability. The results are extrapolated to determine the impact at future technology nodes. The predicted significant performance degradation that variability will cause demonstrates the importance of new circuit or system design techniques to cope with variations in future FPGAs.

On-FPGA Communication Architectures and Design Factors

2006 International Conference on Field Programmable Logic and Applications, 2006

The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with ... more The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. This survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

Wave-pipelined signaling for on-FPGA communication

2008 International Conference on Field-Programmable Technology, 2008

On-FPGA communication is becoming more problematic as the long interconnection performance is det... more On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA. The throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous link. Two circuit designs are

Fault tolerant methods for reliability in FPGAs

2008 International Conference on Field Programmable Logic and Applications, 2008

Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs... more Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.

Throughput maximization for wave-pipelined interconnects using cascaded buffers and transistor sizing

2009 IEEE International Symposium on Circuits and Systems, 2009

ABSTRACT

Compensating for variability in FPGAs by re-mapping and re-placement

2009 International Conference on Field Programmable Logic and Applications, 2009

... [3] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, Parameter varia... more

Implementation of Wave-Pipelined Interconnects in FPGAs

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008

Global interconnection and communication at high clock frequencies are becoming more problematic ... more Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.

Global interconnections in FPGAs

Proceedings of the tenth international workshop on System level interconnect prediction - SLIP '08, 2008

This paper presents a new model for global routings in FP-GAs. The irregular interconnections in ... more This paper presents a new model for global routings in FP-GAs. The irregular interconnections in FPGAs can be generalized as multiple buffered interconnect stages, of which the electrical waveform can be adequately approximated. Based on the model, expressions of delay and fundamental throughput of the interconnections have been derived and validated. They are shown in line with the SPICE and FPGA experimental results. Moreover, the model shows that interconnection throughput can be significantly increased using wave-pipelined signaling instead of the conventional delay-based synchronous approach, as has been demonstrated in our FPGA experiments. We conclude this paper by having a discussion about a strategy to further enhance the interconnect throughput.

Degradation in FPGAs

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10, 2010

Progress in VLSI technology is driven by increasing circuit density through process scaling, but ... more Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for

Combating process variation on FPGAS with a precise at-speed delay measurement method

2008 International Conference on Field Programmable Logic and Applications, 2008

The goal of this PhD project is to devise a way to combat the effect of process variation on prop... more The goal of this PhD project is to devise a way to combat the effect of process variation on propagation delays in modern FPGAs. Through our research, we have devised a novel measurement method that is capable of measuring the delays of components on FPGAs with picosecond timing resolution and fine spatial granularity. The method avoids the use of external

Modelling and compensating for clock skew variability in FPGAs

2008 International Conference on Field-Programmable Technology, 2008

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process par... more As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognisant of within-die performance variability. This paper examines the effect of process variability on the clock resources in FPGA devices. A model of variation in clock skew in FPGA clock networks is presented. Techniques for reducing the impact of variations on the performance of implemented designs are proposed and analysed, demonstrating that skew variation can be reduced by 70% or more through a combination of phase adjustment and clock rerouting. Measurements on a Virtex-5 FPGA validate the feasibility and benefits of the proposed compensation strategies.

Characterisation of FPGA Clock Variability

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process par... more As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic overdesign. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FP-GAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.

Self-characterization of Combinatorial Circuit Delays in FPGAs

2007 International Conference on Field-Programmable Technology, 2007

This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial ci... more This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of lps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-IT FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

A Structured System Methodology for FPGA Based System-on-A-Chip Design

Field-Programmable Custom Computing Machines, 2004

The ever increasing quantities of logic resources combined with heterogeneous integrated performa... more The ever increasing quantities of logic resources combined with heterogeneous integrated performance enhancing primitives in high-end FPGAs creates a design complexity challenge that requires new methodologies to address. We present a structured system based design methodology which aims to increase productivity and exploit reconfigurability in large scale FPGAs. The methodology is exemplified by sonic-on-a-chip, a video image processing system.

A Structured Methodology for System-on-an-FPGA Design

Field-Programmable Logic and Applications, 2004

Increasing logic resources coupled with a proliferation of integrated performance enhancing primi... more Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which requires new methodologies to overcome. This paper presents a structured system based design methodology, centred around the concept of architecture reuse, which aims to increase productivity and exploit the reconfigurability of high-end FPGAs. The methodology is exemplified by

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Field-Programmable Logic and Applications, 2003

The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low... more The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low-power, flexible and adaptable integrated image processing systems. An architecture for a system-on-a-chip solution is proposed, based on reconfigurable computing. The inherent system modularity and the communication infrastructure are targeted at enhancing design productivity and reuse. Power consumption is addressed by a combination of efficient streaming data transfer