Journal of Parallel and Distributed Computing, Feb 1, 1997
Exact array dataflow analysis can be achieved in the genera] case If the only control structurr=s... more Exact array dataflow analysis can be achieved in the genera] case If the only control structurr=s are do-loops andstrurtural ifs, andifloopcounter bound sandarray subscrll)ts are afline expressions of en,glol>mg loop counters au{{ possii>ly some integer ronstants In t!ms paper. we begin the study ofdataflow analysls ofclynarnlc control programs, where arbitrary ifs and whiles are allow7ed In the general case, only be fuzzy PPOPP '
This document is the User's Manual of PIP, a software which solves Parametric Integer Progra... more This document is the User's Manual of PIP, a software which solves Parametric Integer Programming problems. That is, PIP finds the lexicographic minimum of the set of integer points which lie inside a convex polyhedron, when that polyhedron depends linearly on one or more integral parameters.
ACM Transactions on Design Automation of Electronic Systems, 2009
Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband t... more Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband telecommunication algorithms, stringent timing constraints of 4G wireless telecommunication systems require computing-intensive data-driven architectures. Managing the complexity of these systems within the energy constraints of a mobile terminal is becoming a major challenge for designers. System-level low-power policies have been widely explored for generic software-based systems, but data-flow architectures used for high data-rate telecommunication systems feature heterogeneous components that require specific configurations for power management. In this study, we propose an innovative power optimization scheme tailored to self-synchronized data-flow systems. Our technique, based on the synchronous data-flow modeling approach, takes advantage of the latest low-power techniques available for digital architectures. We illustrate our optimization method on a complete 4G telecommunication ...
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple... more In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able to exploit computation in the main memory. While several instantiations of this architecture have been proposed, the question of how to effectively program them with little effort has remained a major challenge. In this paper, we show how to effectively hand-program an intelligent memory architecture at a high level and with very modest effort. We use FlexRAM as a prototype architecture. To program it, we propose a family of high-level compiler directives inspired by OpenMP called CFlex. Such directives enable the processors in memory to execute the program in cooperation with the main processor. In addition, we propose libraries of highly-optimized functions called Intelligent Memory Operations (IMOs). These functions program the processors in memory through CFlex, but make them completely transparent to the programmer. Simulation results show that, with CFlex and IMOs, a server with 64 simple processors in memory runs on average 10 times faster than a conventional server. Moreover, a set of conventional programs with 240 lines on average are transformed into CFlex parallel form with only 7 CFlex directives and 2 additional statements on average.
One of many approaches to better take advantage of parallelism, which has now become mainstream, ... more One of many approaches to better take advantage of parallelism, which has now become mainstream, is the introduction of parallel programming languages. However, parallelism is by nature nondeterministic, and not all parallel bugs can be avoided by language design. This paper proposes a method for guaranteeing absence of data races in the polyhedral subset of clocked X10 programs. Clocks in X10 are similar to barriers, but are more dynamic; the subset of processes that participate in the synchronization can dynamically change at runtime. We construct the happens-before relation for clocked X10 programs, and show that the problem of race detection is undecidable. However, in many practical cases, modern tools are able to find solutions or disprove their existence. We present a set of benchmarks for which the analysis is possible and has an acceptable running time.
Proceedings of the 1986 SIGPLAN symposium on Compiler contruction - SIGPLAN '86, 1986
Asynchronous CALL statements are necessary in order to use more than one processor in current mul... more Asynchronous CALL statements are necessary in order to use more than one processor in current multiprocessors. Detecting CALL statements that may be executed in parallel is one way to fill this need. This approach requires accurate approximations of called procedure effects. This is achieved by using new objects called Region and Ezecution Contezt. An algorithm to find asynchronous CALL statements is given. It involves a new dependence test to compute data dependence graphs, which provides better results than previous ones even when no CALL statements are involved. This method has been implemented in Parafrase and preliminary results are encouraging.
Scientific programs must be transformed and adapted to supercomputers to be executed efficiently.... more Scientific programs must be transformed and adapted to supercomputers to be executed efficiently. Automatic parallelization has been a very active research field for the past few years and effective restructuring compilers have been developed. Although CALL statements are not properly handled by current automatic tools, it has recently been shown that parallel execution of subroutines provides good speedups on multiprocessor machines.
Many present-day microprocessors have flne grain parallelism, be it in the form of a pipeline, of... more Many present-day microprocessors have flne grain parallelism, be it in the form of a pipeline, of multiple functional units, or replicated processors. The efficient use of such architectures depends on the capability of the compiler to schedule the execution of the object code in such a way that most of the available hardware is in use while complying with data dependences. In the case of one simple loop, the schedule may be expressed as an affine form in the loop counter. The coefficient of the loop counter in the schedule is the initiation interval, and gives the mean rate at which loop bodies may be executed. The dependence constraints may be converted to linear inequalities in the coefficients of a closed form schedule, and then solved by classical linear programming algorithms. The resource constraints, however, translate to non-linear constraints. These constraints become linear if the initiation interval is known. This leads to a fast searching algorithm, in which the initiation interval is increased until a feasible solution is found.
Abstract: A standard method,for proving the termination of a flowchart program is to exhibit a ra... more Abstract: A standard method,for proving the termination of a flowchart program is to exhibit a ranking function, i.e., a function from the program states to a well-founded set, which strictly decreases at each program step. Our main contribution is to give an efficient algorithm for the automatic generation of multi-dimensional affine nonnega- tive ranking functions, a restricted class of ranking
This paper addresses the static analysis of an important class of X10 programs, namely those with... more This paper addresses the static analysis of an important class of X10 programs, namely those with finish/async parallelism, and affine loops and array reference structure as in the polyhedral model. For such programs our analysis can certify whenever a program is deterministic or flags races. Our key contributions are (i) adaptation of array dataflow anal-ysis from the polyhedral model to programs with finish/async par-allelism, and (ii) use of the array dataflow analysis result to certify determinacy. We distinguish our work from previous approaches by combining the precise statement instance-wise and array element-wise analysis capability of the polyhedral model with finish/async programs that are more expressive than doall parallelism com-monly considered in the polyhedral literature. We show that our approach is exact (no false negative/positives) and more precise than previous approaches, but is limited to programs that fit the polyhedral model.
Advances in VLSI technology have enabled the implementation of computer architectures based on Pr... more Advances in VLSI technology have enabled the implementation of computer architectures based on Processing-inMemory (PIM) chips. These architectures can help bridge the growing gap between processor and main memory speeds and, as a result, improve the performance of both numeric and symbolic codes. While PIM organization has been extensively studied from the machine organization point of view, the problem of effectively programming this kind of systems has been largely ignored. In this paper, we address how to program FlexRAM, a generalpurpose computer with PIM memory modules. We present CFlex, a family of compiler directives inspired in OpenMP, which enable the development of portable programs. We also explore enhancing the programmability with libraries of functions called Intelligent Memory Operations (IMOs). These libraries are optimized to make use of the PIMs but hide all their complexity. The geometric mean of the speedups achieved for our test suite by a system with one FlexR...
One of many approaches to better take advantage of parallelism, which has now become mainstream, ... more One of many approaches to better take advantage of parallelism, which has now become mainstream, is the introduction of parallel programming languages. However, parallelism is by nature non-deterministic, and not all parallel bugs can be avoided by language design. This paper proposes a method for guaranteeing absence of data races in the polyhedral subset of clocked X10 programs. Clocks in X10 are similar to barriers, but are more dynamic; the subset of processes that participate in the synchronization can dynamically change at runtime. We construct the happens-before relation for clocked X10 programs, and show that the problem of race detection is undecidable. However, in many practical cases, modern tools are able to find solutions or disprove their existence. We present a set of benchmarks for which the analysis is possible and has an acceptable running time.
A memory hierarchyhas coherence problems as soon- -contents of the main memory--iscopied in the -... more A memory hierarchyhas coherence problems as soon- -contents of the main memory--iscopied in the -cache. One asoneofits levels issplit inseveral independent units-which arenot says thatsuch a datum-is present inthecache.Ifa processor p^|ilarl ad-onauMla frnw factorlnwalenr nrd%d%1Qlrc 'MA'dIgQ;lea_ _. equaiiy auivieirUm iUster ieveIs Urp1csws ineciRss.141 solution tothese problems, asfound forinstance inmultiprocessor, multicache systems, istorestore a degree ofinterdependence between such units through asetofhigh
Compiler Optimizations For Scalable Parallel Systems Languages, 2001
While mathematical reasoning is about fixed values, programs are written in term of memory cells,... more While mathematical reasoning is about fixed values, programs are written in term of memory cells, whose contents are changeable values. To reason about programs, the first step is always to abstract from the memory cells to the values they contains at a given point in the execution of the program. This step, which is known as Dataflow Analysis, may use
This document is the User's Manual of PIP, a software which solves Parametric Integer Programming... more This document is the User's Manual of PIP, a software which solves Parametric Integer Programming problems. That is, PIP finds the lexicographic minimum of the set of integer points which lie inside a convex polyhedron, when that polyhedron depends linearly on one or more integral parameters.
This research report presents a non intrusive methodology for building embedded systems energy co... more This research report presents a non intrusive methodology for building embedded systems energy consumption models. The method is based on measurement on real hardware in order to get a quantitative approach that takes into account the full architecture. Based on these measurements, data are grouped into class of instructions and events. These classes can then be reused in software simulators and in high-level source code transformation cost functions for optimizing compilers. The computed power model is much more simpler than previous power models while being accurate at the platform level. The methodology is illustrated using experimental results made on an ARM Integrator platform for which an accurate and full system energy model is build.
Journal of Parallel and Distributed Computing, Feb 1, 1997
Exact array dataflow analysis can be achieved in the genera] case If the only control structurr=s... more Exact array dataflow analysis can be achieved in the genera] case If the only control structurr=s are do-loops andstrurtural ifs, andifloopcounter bound sandarray subscrll)ts are afline expressions of en,glol>mg loop counters au{{ possii>ly some integer ronstants In t!ms paper. we begin the study ofdataflow analysls ofclynarnlc control programs, where arbitrary ifs and whiles are allow7ed In the general case, only be fuzzy PPOPP '
This document is the User's Manual of PIP, a software which solves Parametric Integer Progra... more This document is the User's Manual of PIP, a software which solves Parametric Integer Programming problems. That is, PIP finds the lexicographic minimum of the set of integer points which lie inside a convex polyhedron, when that polyhedron depends linearly on one or more integral parameters.
ACM Transactions on Design Automation of Electronic Systems, 2009
Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband t... more Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband telecommunication algorithms, stringent timing constraints of 4G wireless telecommunication systems require computing-intensive data-driven architectures. Managing the complexity of these systems within the energy constraints of a mobile terminal is becoming a major challenge for designers. System-level low-power policies have been widely explored for generic software-based systems, but data-flow architectures used for high data-rate telecommunication systems feature heterogeneous components that require specific configurations for power management. In this study, we propose an innovative power optimization scheme tailored to self-synchronized data-flow systems. Our technique, based on the synchronous data-flow modeling approach, takes advantage of the latest low-power techniques available for digital architectures. We illustrate our optimization method on a complete 4G telecommunication ...
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple... more In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able to exploit computation in the main memory. While several instantiations of this architecture have been proposed, the question of how to effectively program them with little effort has remained a major challenge. In this paper, we show how to effectively hand-program an intelligent memory architecture at a high level and with very modest effort. We use FlexRAM as a prototype architecture. To program it, we propose a family of high-level compiler directives inspired by OpenMP called CFlex. Such directives enable the processors in memory to execute the program in cooperation with the main processor. In addition, we propose libraries of highly-optimized functions called Intelligent Memory Operations (IMOs). These functions program the processors in memory through CFlex, but make them completely transparent to the programmer. Simulation results show that, with CFlex and IMOs, a server with 64 simple processors in memory runs on average 10 times faster than a conventional server. Moreover, a set of conventional programs with 240 lines on average are transformed into CFlex parallel form with only 7 CFlex directives and 2 additional statements on average.
One of many approaches to better take advantage of parallelism, which has now become mainstream, ... more One of many approaches to better take advantage of parallelism, which has now become mainstream, is the introduction of parallel programming languages. However, parallelism is by nature nondeterministic, and not all parallel bugs can be avoided by language design. This paper proposes a method for guaranteeing absence of data races in the polyhedral subset of clocked X10 programs. Clocks in X10 are similar to barriers, but are more dynamic; the subset of processes that participate in the synchronization can dynamically change at runtime. We construct the happens-before relation for clocked X10 programs, and show that the problem of race detection is undecidable. However, in many practical cases, modern tools are able to find solutions or disprove their existence. We present a set of benchmarks for which the analysis is possible and has an acceptable running time.
Proceedings of the 1986 SIGPLAN symposium on Compiler contruction - SIGPLAN '86, 1986
Asynchronous CALL statements are necessary in order to use more than one processor in current mul... more Asynchronous CALL statements are necessary in order to use more than one processor in current multiprocessors. Detecting CALL statements that may be executed in parallel is one way to fill this need. This approach requires accurate approximations of called procedure effects. This is achieved by using new objects called Region and Ezecution Contezt. An algorithm to find asynchronous CALL statements is given. It involves a new dependence test to compute data dependence graphs, which provides better results than previous ones even when no CALL statements are involved. This method has been implemented in Parafrase and preliminary results are encouraging.
Scientific programs must be transformed and adapted to supercomputers to be executed efficiently.... more Scientific programs must be transformed and adapted to supercomputers to be executed efficiently. Automatic parallelization has been a very active research field for the past few years and effective restructuring compilers have been developed. Although CALL statements are not properly handled by current automatic tools, it has recently been shown that parallel execution of subroutines provides good speedups on multiprocessor machines.
Many present-day microprocessors have flne grain parallelism, be it in the form of a pipeline, of... more Many present-day microprocessors have flne grain parallelism, be it in the form of a pipeline, of multiple functional units, or replicated processors. The efficient use of such architectures depends on the capability of the compiler to schedule the execution of the object code in such a way that most of the available hardware is in use while complying with data dependences. In the case of one simple loop, the schedule may be expressed as an affine form in the loop counter. The coefficient of the loop counter in the schedule is the initiation interval, and gives the mean rate at which loop bodies may be executed. The dependence constraints may be converted to linear inequalities in the coefficients of a closed form schedule, and then solved by classical linear programming algorithms. The resource constraints, however, translate to non-linear constraints. These constraints become linear if the initiation interval is known. This leads to a fast searching algorithm, in which the initiation interval is increased until a feasible solution is found.
Abstract: A standard method,for proving the termination of a flowchart program is to exhibit a ra... more Abstract: A standard method,for proving the termination of a flowchart program is to exhibit a ranking function, i.e., a function from the program states to a well-founded set, which strictly decreases at each program step. Our main contribution is to give an efficient algorithm for the automatic generation of multi-dimensional affine nonnega- tive ranking functions, a restricted class of ranking
This paper addresses the static analysis of an important class of X10 programs, namely those with... more This paper addresses the static analysis of an important class of X10 programs, namely those with finish/async parallelism, and affine loops and array reference structure as in the polyhedral model. For such programs our analysis can certify whenever a program is deterministic or flags races. Our key contributions are (i) adaptation of array dataflow anal-ysis from the polyhedral model to programs with finish/async par-allelism, and (ii) use of the array dataflow analysis result to certify determinacy. We distinguish our work from previous approaches by combining the precise statement instance-wise and array element-wise analysis capability of the polyhedral model with finish/async programs that are more expressive than doall parallelism com-monly considered in the polyhedral literature. We show that our approach is exact (no false negative/positives) and more precise than previous approaches, but is limited to programs that fit the polyhedral model.
Advances in VLSI technology have enabled the implementation of computer architectures based on Pr... more Advances in VLSI technology have enabled the implementation of computer architectures based on Processing-inMemory (PIM) chips. These architectures can help bridge the growing gap between processor and main memory speeds and, as a result, improve the performance of both numeric and symbolic codes. While PIM organization has been extensively studied from the machine organization point of view, the problem of effectively programming this kind of systems has been largely ignored. In this paper, we address how to program FlexRAM, a generalpurpose computer with PIM memory modules. We present CFlex, a family of compiler directives inspired in OpenMP, which enable the development of portable programs. We also explore enhancing the programmability with libraries of functions called Intelligent Memory Operations (IMOs). These libraries are optimized to make use of the PIMs but hide all their complexity. The geometric mean of the speedups achieved for our test suite by a system with one FlexR...
One of many approaches to better take advantage of parallelism, which has now become mainstream, ... more One of many approaches to better take advantage of parallelism, which has now become mainstream, is the introduction of parallel programming languages. However, parallelism is by nature non-deterministic, and not all parallel bugs can be avoided by language design. This paper proposes a method for guaranteeing absence of data races in the polyhedral subset of clocked X10 programs. Clocks in X10 are similar to barriers, but are more dynamic; the subset of processes that participate in the synchronization can dynamically change at runtime. We construct the happens-before relation for clocked X10 programs, and show that the problem of race detection is undecidable. However, in many practical cases, modern tools are able to find solutions or disprove their existence. We present a set of benchmarks for which the analysis is possible and has an acceptable running time.
A memory hierarchyhas coherence problems as soon- -contents of the main memory--iscopied in the -... more A memory hierarchyhas coherence problems as soon- -contents of the main memory--iscopied in the -cache. One asoneofits levels issplit inseveral independent units-which arenot says thatsuch a datum-is present inthecache.Ifa processor p^|ilarl ad-onauMla frnw factorlnwalenr nrd%d%1Qlrc 'MA'dIgQ;lea_ _. equaiiy auivieirUm iUster ieveIs Urp1csws ineciRss.141 solution tothese problems, asfound forinstance inmultiprocessor, multicache systems, istorestore a degree ofinterdependence between such units through asetofhigh
Compiler Optimizations For Scalable Parallel Systems Languages, 2001
While mathematical reasoning is about fixed values, programs are written in term of memory cells,... more While mathematical reasoning is about fixed values, programs are written in term of memory cells, whose contents are changeable values. To reason about programs, the first step is always to abstract from the memory cells to the values they contains at a given point in the execution of the program. This step, which is known as Dataflow Analysis, may use
This document is the User's Manual of PIP, a software which solves Parametric Integer Programming... more This document is the User's Manual of PIP, a software which solves Parametric Integer Programming problems. That is, PIP finds the lexicographic minimum of the set of integer points which lie inside a convex polyhedron, when that polyhedron depends linearly on one or more integral parameters.
This research report presents a non intrusive methodology for building embedded systems energy co... more This research report presents a non intrusive methodology for building embedded systems energy consumption models. The method is based on measurement on real hardware in order to get a quantitative approach that takes into account the full architecture. Based on these measurements, data are grouped into class of instructions and events. These classes can then be reused in software simulators and in high-level source code transformation cost functions for optimizing compilers. The computed power model is much more simpler than previous power models while being accurate at the platform level. The methodology is illustrated using experimental results made on an ARM Integrator platform for which an accurate and full system energy model is build.
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