Papers by Mohamed Elmasry
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1989
Absfmcf-A novel design methodology for automated mapping of DSP algorithms into VLSI architecture... more Absfmcf-A novel design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units and parallelism of the architecture are all explored in the design space. The synthesized architecture is a multi-bus multi-functional unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably over other synthesis techniques.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1993
A relaxed LP model, which simultaneously schedules and allocates functional units and registers, ... more A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing exploration of optimal synthesized architectures since it is well known that early architectural decisions have the greatest impact on the final design. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Polyhedral theory was used to formulate constraints that decreased the size of the search space, thus improving integer programming solution efficiency. Execution times are an order-of-magnitude faster than previous research that uses heuristic techniques. This research breaks new ground by 1) simultaneously scheduling and allocating in practical execution times, 2) guaranteeing globally optimal solutions for a specific objective function, and 3) providing a polynomial run-time algorithm for solving some instances of this NP-complete problem.
Circuit techniques for CMOS low-power high-performance multipliers
IEEE Journal of Solid-state Circuits, 1996
Abstrucl- In this paper we present circuit techniques for CMOS low-power high-performance multipl... more Abstrucl- In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8- pm CMOS (in BiCMOS) technology. The complementary ...
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
... In(k) = number of distinct inputs(~ I ) to k, Out(k) = number of distinct Outputs(= 1). ~z ~ ... more ... In(k) = number of distinct inputs(~ I ) to k, Out(k) = number of distinct Outputs(= 1). ~z ~ ~(~z) means that asmp(kz)~ jZ<alap(kZ). kZ 6 op( CZ,LZ)[6] means that operation kz requires Cz csteps to produce an output data value and accepts new input data every Lz csteps. For ...
IEEE Journal of Solid-state Circuits, 1992
An integer programming (IP) model, which simultaneously schedules and allocates functional units,... more An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and buses, is presented for synthesizing cost-contrained globally optimal architectures. This research is important for industry by providing optimal schedules that minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high-performance architectures. A mathematical IP model of the architectural synthesis problem is formulated. A subset of the constraints is transformed into the node-packing problem and integral facets are extracted and generalized. Other constraints are tightened or mapped into the knapsack problem and facets are extracted and generalized. Area-delay cost functions are minimized using branch and bound on the resulting IP model. Globally optimal architectures are synthesized in faster CPU times than previous research. This research breaks new ground by: 1) providing industry with interconnect-optimized architectures since interconnect is seen as the key to high performance; 2) synthesizing globally optimal architectures in faster execution times than current heuristic techniques; 3) supporting interfaces to asynchronous and analog interfaces; and 4) supporting piecewise linear area-delay cost functions.
A relaxed LP model, which simultaneously schedules and allocates functional units and registers, ... more A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Some integral facets of this polytope were extracted and generalized to produce integral solutions using the simplex algorithm without the need to branch and bound. Execution times are faster by an order of magnitude than previous research which makes use of heuristic techniques. This research breaks ground by simultaneously scheduling and allocating with practical execution times; guaranteeing globally optimal solutions for a specific objective function; and providing a polynomial runtime algorithm for solving this NP-complete problem.>
The current research investigates the use of acid and enzyme hydrolysis to produce glucose from p... more The current research investigates the use of acid and enzyme hydrolysis to produce glucose from pretreated rice straw, banana plant waste and corn cob, as a lignocellulosic materials, to be a source for ethanol production. The agricultural biomasses were first tested, then a laboratory experimental set-up was designed in order to perform the necessary conversions. The biomass materials were characterized to contain 57.46-85.28% holocellulose and 14.55-26.12% lignin. Conversion of the cellulose to glucose was achieved by pre-treatment method for the agricultural residues first applying chemical pulping and steam explosion method as well as microwave treatment then followed by two processes, namely acid hydrolysis and enzyme hydrolysis. Sulfuric acid, 5%, was used in acid hydrolysis and Trichoderma reesei cellulases in enzyme hydrolysis. These experiments demonstrated that glucose concentration differs according to the type of pre-treatment and type of hydrolysis. Conversion of the glucose to ethanol during fermentation was accomplished by the action of yeasts from Saccharomyces cerevisiae. Ethanol production in the culture sample was monitored using gas chromatography. The results indicate that ethanol can be made from the above mentioned residues in a different yield according to the pre-treatment and the glucose produced from the hydrolysis method.
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Papers by Mohamed Elmasry