Papers by Masahiro Fujita
Proceedings of the 8th international symposium on System synthesis - ISSS '95, 1995
This paper describes the application of a measurement based p ower analysis technique for an embe... more This paper describes the application of a measurement based p ower analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Signicant points of dierence have been observed b etween this model and the ones developed e arlier for some general-purpose commercial microprocessors . In particular, the eect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be p acked into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed t o r e duce the energy consumed by DSP software. Energy reductions varying from 11% to 56% have been observed for several example programs. These energy savings are r e al and have been veried through physical measurement.
Proceedings of the 33rd annual conference on Design automation conference - DAC '96, 1996
This paper presents our experience o n domain-specic high-level modeling and synthesis for Fujits... more This paper presents our experience o n domain-specic high-level modeling and synthesis for Fujitsu ATM switch design. We propose a high-level design methodology using VHDL, where A TM switch architectural features are c onsidered during behavior modeling, and a high-level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate-level implementation. Since the specic ATM switch architecture i s i n c orporated into both modeling and synthesis phases, a high-quality design is eciently derived. The synthesis results show that given the design constraints, the proposed high-level design methodology can produce a gate-level implementation by MEBS with about 15% area r e duction in shorter design cycle when compared with manual design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
Power is becoming a critical constraint for designing embedded applications. Current power analys... more Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded DSP processor based on physical current measurements. Signi cant points of di erence have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general-purpose commercial microprocessors 1, 2]. In particular, the e ect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual-memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above e ects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the e ectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been veri ed through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modi cation, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modi ed programs either improve or remain unchanged.
International Conference on Computer Design, 1993
We present a method which accepts Interval Temporal Logic (ITL) formulas as specification and aut... more We present a method which accepts Interval Temporal Logic (ITL) formulas as specification and automatically generates state machines. The specification in ITL can also be used as a con- straint for a state machine which is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further pro-
Lecture Notes in Computer Science
A data path verifier for register transfer level is presented in this paper. The verifier checks ... more A data path verifier for register transfer level is presented in this paper. The verifier checks if all the operations and the data transfers in a behavioral description can be realized on a given data path without any scheduling conflicts. Temporal logic based language Tokio is adopted as a behavioral description language in this verifier. In Tokio, designers can directly describe concurrent behaviors controlled by more than one finite state machine without unfolding parallelism. The verifier checks for the consistency between a behavior and a structure automatically and lightens the load of designers. The actual LSI chip which consists of 18,000 gates on CMOS gate array has been successfully verified. This verifier is concluded to have the ability to verify practical hardware design.
IEEE/ACM International Conference on Computer-Aided Design
In this paper, we consider a redesign technique applicable to combinational circuits implemented ... more In this paper, we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Boolean-constraint problem and give a BDD-based algorithm to check the feasibility of redesign.
Proceedings of the 14th international symposium on Systems synthesis - ISSS '01, 2001
This paper introduces SpecC language, a system level description language based on C, and its con... more This paper introduces SpecC language, a system level description language based on C, and its consortium, SpecC Technology Open Consortium (STOC). Currently SpecC language version 1.0 is publicly available. SpecC technology covers SpecC-based design "methodology" as well as SpecC language itself. In this paper not only SpecC language but also SpecC-based design methodology are briefly discussed. The SpecC language specification working group (LSWG) under STOC is discussing on SpecC version 2.0. We also give a summary of the discussions being made by LSWG targeting version 2.0. We plan to formally release version 2.0 in the beginning of 2002. The main goal is to precisely and exactly define the formal semantics of SpecC language especially on the semantics relating to parallel and concurrent statements and event control mechanisms. These are the issues on which SpecC version 1.0 does not give clear and concise semantics. With these clarifications given by SpecC version 2.0, varieties of supporting tools for SpecC can consistently and easily be developed.
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003
Asynchronous speed independent (SI) circuits based on an unbounded gate delay model often suffer ... more Asynchronous speed independent (SI) circuits based on an unbounded gate delay model often suffer from high area penalty. It happens due to the lack of efficient global optimization. This paper presents a boolean optimization method based on tranduction method to optimize asynchronous SI circuits while preserving hazard-freeness.
IPSJ Transactions on System LSI Design Methodology, 2010
When designing today's highly complicated systems consisting of several hardware and software mod... more When designing today's highly complicated systems consisting of several hardware and software modules, it is essential to estimate the performance such as worst-case or best-case execution time in early design stages. Such estimation is essential to explore architecture and hardware/software partitioning in system-level design. A maximum execution time estimated topologically without considering false-paths is longer than the real. In this paper, we propose an static estimation method of maximum execution time in system-level designs, considering false-paths. Also, we adopt an approximation approach in order to avoid the path explosion problem. The experimental results show that our method can provide much smaller estimated maximum execution time than the method without considering false-paths. At the same time, the results show us that the maximum execution time can be estimated to a very small range, by applying both simulation-based method and our static method.
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
In this paper, we propose a new methodology to integrate circuit transformation into routing. Mor... more In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire reconnection simultaneously. To accomplish this, we introduce a new logic representation that implements all possible wire reconnections implicitly by enhancing global flow optimization techniques. Since our method takes into account circuit transformation during routing phase where the accurate physical information is available, we can obtain better results than the conventional routing algorithms. In addition, we can succeed in routing even if other routers like rip-up and reroute methods fail. The algorithm has been implemented and the experimental results are presented. We believe this is the first approach which combines them completely.
An array of nonuniform semiconductor diode lasers with supermode control for achieving a single-l... more An array of nonuniform semiconductor diode lasers with supermode control for achieving a single-lobed farfield pattern is described. This is accomplished by spatially segregating the fundamental supermode from the other supermodes, tailoring the spatial gain profile as as to favor the fundamental supermode, and sufficiently increasing the intechannel coupling so as to bring about single-lobed farfield operation. In a preferred embodiment, this is achieved in a shallowly proton implanted, tailored gain, chirped laser array in which the widths of the lasers are varied linearly across the array.
International Symposium on Quality Electronic Design, Mar 16, 2009
Rule-based equivalence checking of system-level design descriptions proves the equivalence of two... more Rule-based equivalence checking of system-level design descriptions proves the equivalence of two system-level design descriptions by applying the equivalence rules in a bottom-up manner. Since the previous work derives the equivalence of the internal variables based on their names, the method often fails to prove the equivalence when the variable names are changed. This paper proposes a method for improving the accuracy of the rule-based equivalence checking by identifying potential internal equivalences using random simulation. Experimental results using an example design show that the proposed method can prove the equivalence of the designs before and after a practical design optimization.
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
For a variety of signal processing applications polynomials are implemented in circuits. Recent w... more For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware cost as well as delay compared to previous approaches like Horner form or Common Sub-expression Elimination (CSE). This work 1) proposes a formal model for single-and multi-polynomial factorization and 2) handles optimization as a constraint solving problem using an explicit cost function. By this, optimal datapath implementations with respect to the cost function are determined. Compared to recent state-of-the-art heuristics an average reduction of area and critical path delay is achieved.
2009 International Conference on Communications, Circuits and Systems, 2009
This paper presents our study on rule-based equivalence checking of system-level design descripti... more This paper presents our study on rule-based equivalence checking of system-level design descriptions. The rule-based equivalence checking proves the equivalence of two system-level design descriptions by applying equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative equivalence rules. Since our equivalence checking method is based on potential internal equivalences identified by using random simulation, we also present how to prove the equivalence based on such potential internal equivalences. Finally, we explain our implementation of the rule-based equivalence checker and demonstrate its feasibility and efficiency using an example design.
IPSJ Transactions on System LSI Design Methodology, 2011
This paper presents an exact method which finds the minimum factored form of an incompletely spec... more This paper presents an exact method which finds the minimum factored form of an incompletely specified Boolean function. The problem is formulated as a Quantified Boolean Formula (QBF) and is solved by general-purpose QBF solver. We also propose a novel graph structure, called an X-B (eXchanger Binary) tree, which compactly and implicitly enumerates binary trees. Leveraged by this graph structure, the factoring problem is transformed into a QBF. Using three sets of benchmark functions: artificially-created, randomly-generated and ISCAS 85 benchmark functions, we empirically demonstrate the quality of the solutions and the runtime complexity of the proposed method.
Journal on Satisfiability, Boolean Modeling and Computation, 2008
Program slicing is a software-analysis technique that generates System Dependence Graphs (SDGs) b... more Program slicing is a software-analysis technique that generates System Dependence Graphs (SDGs) by which dependencies among program statements can be identified through their traversal. We have developed a program slicing tool for SpecC, a C-based system level design language for hardware/software co-designs, on top of a program slicer for C/C++. This program slicing tool can generate SDGs from any combined descriptions in C, C++, and SpecC, and can be used to analyze design descriptions for hardware/software co-designs uniformly and smoothly in all the combined descriptions. In this paper, after reviewing our program slicer that generates SDGs, we present verification and synthesis techniques for hardware/software co-designs through various analyses on SDGs and generations of SAT/ILP problems from them. For analysis and verification of the combined descriptions, we examine SDGs statically by traversing them with SAT/ILP solvers as verification engines. With this method, many static checks can be efficiently realized even if the target design descriptions are fairly large. We first present techniques for checking synchronization among concurrent processes described in SpecC through symbolic analysis on SDGs. The techniques could verify the synchronization of MPEG4 descriptions with about 48,000 lines within 10 seconds. The techniques can be applied to automatic conversions between sequential and parallel computations. One such application to automatic program serialization is presented. By using the technique for automatic program serialization, we could serialize Vocoder descriptions with about 10,000 lines in around 1 minute. As for synthesis from the combined descriptions, we present an optimal code generation method based on SAT formulation. It can generate codes for reconfigurable processors with minimum code lengths. The sizes of problems as SAT formulation range from 10,000 to 100,000 variables and 100,000 to 500,000 clauses for the largest configurations. With appropriate uses of the state-of-the-art SAT solvers and related tools, we show that fairly practical sizes of verification and synthesis problems can be solved by analyzing SDGs generated from the combined descriptions.
Proceedings of the 37th conference on Design automation - DAC '00, 2000
This paper describes a novel formal verification approach for equivalence checking of small, asse... more This paper describes a novel formal verification approach for equivalence checking of small, assembly-language routines for digital signal processors (DSP). By combining control-flow analysis, symbolic simulation, automatic decision procedures, and some domainspecific optimizations, we have built an automatic verification tool that compares structurally similar DSP assembly language routines. We tested our tool on code samples taken from a real application program and discovered several previously unknown bugs automatically. Runtime and memory requirements were reasonable on all examples. Our approach should generalize easily for multiple DSP architectures, eventually allowing comparison of code for two different DSPs (e.g., to verify a port from one DSP to another) and handling more complex DSPs (e.g. statically-scheduled, VLIW).
J. Univers. Comput. Sci., 2007
System Dependence Graph (SDG) is a graph representation which shows dependencies among statements... more System Dependence Graph (SDG) is a graph representation which shows dependencies among statements / expressions in a design. In this paper, we propose a new HW/SW co-design methodology based on SDG. In our method, any combination of C / C++ / SpecC descriptions is acceptable as input designs so that design functions can be specified flexibly. First, the input descriptions are analyzed and verified with static but partially dynamic program checking methods by traversing SDG. With those methods, large descriptions can be processed. Next, those designs are divided into HW and SW parts. In this step, SDGs are fully utilized to insert parallelism into the designs, and it enables flexible HW/SW partitioning. The HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. Finally, the generated RTL descriptions together with the SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Al...
IFIP Advances in Information and Communication Technology, 2015
In this chapter, we propose methods for correcting gate-level designs by identifying appropriate ... more In this chapter, we propose methods for correcting gate-level designs by identifying appropriate logic functions for internal gates. We introduce programmable circuits, such as look up table (LUT) and multiplexer (MUX) to the circuits under debugging, in order to formulate the correction processes mathematically. There are two steps in the proposed methods. The first one is to identify sets of gates and their appropriate inputs whose functions are to be modified. The second one is to actually identify logic functions for the correction by solving QBF (Quantified Boolean Formula) problems with repeated application of SAT solvers. There are a number of bugs which cannot be corrected unless the inputs of the gates to be modified are changed from the original ones, and the selection of such additional inputs is a key for effective debugging. We show a couple of methods by which appropriate inputs to the gates can be efficiently identified. Experimental results for each such a method as well as their combinations targeting benchmark circuits as well as industrial ones are shown.
IEICE Transactions on Information and Systems, 2009
Equivalence checking is one of the most important issues in VLSI design to guarantee that bugs do... more Equivalence checking is one of the most important issues in VLSI design to guarantee that bugs do not enter designs during optimization steps or synthesis steps. In this paper, we propose a new word-level equivalence checking method between two models before and after highlevel synthesis or behavioral optimization. Our method converts two given designs into RTL models which have same datapaths so that behaviors by identical control signals become the same in the two designs. Also, functional units become common to the two designs. Then word-level equivalence checking techniques can be applied in bit-level accuracy. In addition, we propose a rule-based equivalence checking method which can verify designs which have complicated control structures faster than existing symbolic simulation based methods. Experimental results with realistic examples show that our method can verify such designs in practical periods.
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Papers by Masahiro Fujita