Papers by Marie-lise Flottes
Design, Automation, and Test in Europe, Apr 16, 2007
Asian Test Symposium, Nov 22, 2015
International audienc
As any other circuits, secure devices need to be tested to ensure their reliability. Nevertheless... more As any other circuits, secure devices need to be tested to ensure their reliability. Nevertheless, test infrastructures, such as JTAG or scan chains, can maliciously be used to steal secret data stored or processed in secure devices. In this paper, we explore a lightweight solution to protect JTAG access based on a challenge-response authentication protocol. A JTAGauthentication dedicated IP is presented. Design alternatives for quick IP plug-and-play, security, area and test time optimization are presented and evaluated.
In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wal... more In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.
Crypto-processors are the target of attacks. For instance, an attacker may exploit facilities off... more Crypto-processors are the target of attacks. For instance, an attacker may exploit facilities offered by scan chains to retrieve embedded secret data closely related to the key. However, scan design is the most popular and efficient method to test circuit. The goal of the technique proposed here is to preserve test efficiency, diagnostic and debug while counteracting security threats. This solution relies on using the secret key already stored in the circuit under test in order to encrypt test patterns by adding extra blocks ciphers. Both control and observed test data are thus unusable without the knowledge of the key.
Full scan is the most widely accepted and used DfT approach for large sequential machines. Nevert... more Full scan is the most widely accepted and used DfT approach for large sequential machines. Nevertheless, in very dedicated cases it cannot be used mainly due to performance reasons as for example in high performance deeply pipelined CPU units. In this case full scan approach has to be replaced by partial scan. When trying to apply LogicBIST on partially scanned machines, the initialization problem of non-scan elements has to be solved. In this paper, we propose a nearly optimal algorithm to obtain a minimum set of memory elements to be initialized enabling to solve this initialization problem.
The present paper describes the CRTC and EuNICE-Test project actions and outcomes. The original i... more The present paper describes the CRTC and EuNICE-Test project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and remote experiments. This objective is fully fulfilled and we have now, in Europe, five centers of competence able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centers propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode.
An efficient solution for test pattern generation based on a switch-level description of complex ... more An efficient solution for test pattern generation based on a switch-level description of complex CMOS circuits is presented. To obtain gate-level speeds and to test realistic CMOS failures, this mixed-level approach recommends structural and functional grading during the preprocessing phase. Conducting path analysis, relaxation algorithms, and truth-table analysis all contribute to functional grading. Results show that the time required for these additional preprocessing steps is close to negligible compared to total CPU time. During test pattern generation (TPG), fault injection can be performed at switch level with precise knowledge of CMOS technology, while the propagation and backtrace steps are applied to the circuit functional model. Thus, classical TAG algorithms can be used. Two learning techniques that mainly deal with the fault injection step and are compatible with most of the other published techniques are introduced. Their use is optional in this mixed-level approach, but they can significantly speed up TPG.<<ETX>>
Cette these traite des relations de test dans les circuits cmos. Ce type de relation permet de re... more Cette these traite des relations de test dans les circuits cmos. Ce type de relation permet de reduire par equivalence ou dominance des ensembles de pannes. Une etude bibliographique presente l'utilisation de ces relations sur des ensembles de pannes de collage affectant des circuits modelises au niveau porte. L'inefficacite de ces modeles classiques pour representer correctement certaines particularites de la technologie cmos (portes de transmission, effets sequentiels ou analogiques de certains types de pannes) et l'inflation du nombre de modeles et de sites de fautes qui en decoule nous ont amene a reconsiderer le probleme pour des circuits representes au niveau interrupteur. Apres une presentation des differents modeles que nous avons choisi d'utiliser, nous proposons une base theorique permettant d'analyser les relations de test liant des pannes de collage, stuck-off, stuck-on, coupure et court-circuit. Plusieurs relations sont alors demontrees. Cette etude est conclue par la definition d'un ensemble de points de controle dans les reseaux de transistors puis dans les circuits ou plusieurs niveaux de modelisation peuvent etre utilises simultanement. Enfin, une application est proposee sous la forme d'un generateur de listes de pannes minimisees. La presentation de ce logiciel dans le contexte d'un systeme complet de generation d'ensemble de test permet d'en illustrer l'utilisation
An overview is presented of the different possibilities which allow the implementation of switch-... more An overview is presented of the different possibilities which allow the implementation of switch-level test pattern production for CMOS macrocells. A discussion is presented of fault modeling, fault list generation, circuit modeling and fault equivalence. Switch-level fault simulation is outlined along with switch-level ATPG (automatic test pattern generation).<<ETX>>
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Papers by Marie-lise Flottes