Abstract—We consider the extent to which the bit-level repre-sentation of variables can be used t... more Abstract—We consider the extent to which the bit-level repre-sentation of variables can be used to optimize hardware gener-ated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to prede-termine min/max ranges for variables to reduce the bitwidth re-quired to represent variables in hardware. Bitmask analysis char-acterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don’t-cares permit hard-ware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analy-sis in terms of their potential to impact area and speed of HLS-generated hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level optimizations in HLS based on static analysis reduce circuit area by 9%, on av-erage, while additional optimizations...
Abstract—We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi... more Abstract—We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core processors. In the coarse-grained approach, sets of design signals are assigned to different processor cores and routed concurrently. Communica-tion between cores is through the MPI (message passing interface) communications protocol. In the fine-grained approach, the task of routing an individual load pin on a signal is parallelized using threads. Specifically, as FPGA routing resources are traversed during maze expansion, delay calculation, costing and priority queue insertion for these resources execute concurrently. The proposed techniques provide deterministic/repeatable results. Moreover, the coarse and fine-grained approaches are not mutu-ally exclusive and can be used in tandem. Results show that on a 4-core processor, the techniques improve router run-time by ∼2.1×, on average, with no significant impact on circuit speed performance or interconnect resource usage. I.
Embedded system designers can achieve energy and performance benefits by using dedicated hardware... more Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, im-plementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelera-tor design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incremen-tally migrate portions of the program to hardware accelerators im-plemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodol-ogy and system architecture, and discusses ongoing work on pro-filing, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Abstract—In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augment... more Abstract—In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some onchip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles. I.
With the ever-increasing complexity of integrated circuits, the elimination of all design errors ... more With the ever-increasing complexity of integrated circuits, the elimination of all design errors before fabrication is becoming more difficult. This increases the need to find design errors in chips after fabrication. This task, termed post-silicon debug, can be made easier if it is possible to obtain a trace of states that leads to a known state. BackSpace, a proposal for a new debug infrastructure which provides such a trace has been recently presented. BackSpace combines formal analysis with on-chip instrumentation. In this thesis, we show that BackSpace can be made practical by modifying the architecture and debug flow to address the area overhead, and also by addressing on-chip realities such as non-determinism and signal propagation delay. Additionally, this thesis describes a proof-of-concept implementation of a complex processor instrumented with the debug architecture and shows that BackSpace can produce traces hundreds of cycles long. Our results indicate that the area overhead of the breakpoint circuit, a main component of the debug architecture, can be reduced to 5% for our prototype, while still allowing the debug flow to create state-accurate traces. was done independently, while some of it was done in collaboration with Flavio De Paula. The research for Chapters 2 and 3 was performed independently from Flavio's research. Flavio made several contributions to Chapter 4. He was responsible for the pre-image computation software running on the PC connected to the prototype. Additionally, he created a mailbox communication protocol that is used to enable communication between the PC and the FPGA prototype. Flavio wrote the code that uses the mailbox communication protocol on the PC side, but not on the prototype side. Although I was responsible for implementing the OpenRISC 1200 in hardware, Flavio eased the process by first successfully simulating its operation in software. Additionally, Flavio cross-compiled the code for the benchmarks which ran on the OpenRISC 1200. Two papers and two demonstrations have resulted from our work on BackSpace. The two papers both contain material written by Flavio de Paula, Dr.
2008 Formal Methods in Computer-Aided Design, 2008
IC technology continues to closely follow Moore's Law, while the ability to verify designs lags b... more IC technology continues to closely follow Moore's Law, while the ability to verify designs lags behind. The International Technology Roadmap for Semiconductors (ITRS) predicts production of chips using 16nm technology already by 2015, but the verification gap, i.e., advancements in verification technology not keeping up with advancements in design technology, seems to be also increasing at a fast pace. A recent study shows a drop of more than 10 percentage points in the number of 1 st-silicon success from 2002 through 2009. By 2007, more than two-thirds of chips had to be respun due to bugs. The increasing verification gap is to blame. Unfortunately, because more bugs are slipping into the fabricated chip, post-silicon debug is the only way to catch them. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. The focus of post-silicon debug is design errors, whereas traditional VLSI test focuses on random manufacturing defects on each fabricated chip. Post-silicon debug currently consumes more than half of the total verification schedule on typical large designs, and the problem is growing worse. The general problem of post-silicon debug is broad and multi-faceted, spurring a diverse variety of research. In this thesis, I focus on one of the most fundamental tasks: getting an execution trace of on-chip signals for many cycles leading up to an observed bug or crash. Until such a trace is obtained, further debugging is essentially impossible, as there is no way to know what happened on the chip. However, the ever-increasing chip complexity compounded with new features that add non-determinism makes computing accurate traces extremely difficult.
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based... more We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based logic blocks, multiplier/DSP blocks and block RAMs. Specifically, we adapt a state-of-the-art ASIC-based analytical placer to target FPGAs with heterogeneous blocks located at discrete locations throughout the fabric. Our placer also handles macros of LUT-based blocks with specific layout requirements, such as carry chains. Results show that our placer delivers a 4× speedup, on average, compared to Altera's non-timing driven flow, at the cost of a 5% increase in postrouted wirelength, and an 11× speedup compared to Altera's timing-driven flow, at the cost of a 4% increase in post-routed wirelength and a 9% reduction in maximum operating frequency. We also compare with an academic simulated annealing-based placer and demonstrate a 7.4× runtime advantage with 6% better placement quality.
2011 21st International Conference on Field Programmable Logic and Applications, 2011
We propose a new FPGA routing approach that, when combined with a low-cost architecture change, r... more We propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no increase in critical path delay. Our approach begins with traditional PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. Our approach points to a new research direction: reducing FPGA CAD run-time by exploring FPGA architectures and algorithms together.
2008 Ninth International Workshop on Microprocessor Test and Verification, 2008
In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with s... more In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some onchip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles.
2010 International Conference on Field-Programmable Technology, 2010
We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core pro... more We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core processors. In the coarse-grained approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the MPI (message passing interface) communications protocol. In the fine-grained approach, the task of routing an individual load pin on a signal is parallelized using threads. Specifically, as FPGA routing resources are traversed during maze expansion, delay calculation, costing and priority queue insertion for these resources execute concurrently. The proposed techniques provide deterministic/repeatable results. Moreover, the coarse and fine-grained approaches are not mutually exclusive and can be used in tandem. Results show that on a 4-core processor, the techniques improve router run-time by ∼2.1×, on average, with no significant impact on circuit speed performance or interconnect resource usage.
2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013
Embedded system designers can achieve energy and performance benefits by using dedicated hardware... more Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source highlevel synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Formal-Analysis-Based Trace Computation for Post-Silicon Debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
Abstract This paper presents a post-silicon debug methodology that provides a means to rewind, or... more Abstract This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is ...
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We present parallelization and heuristic techniques to reduce the run-time of field-programmable ... more We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over $3\times$ speedup versus a sequential baseline. In our parallel approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the message passing interface communications protocol. We propose a
Abstract—We consider the extent to which the bit-level repre-sentation of variables can be used t... more Abstract—We consider the extent to which the bit-level repre-sentation of variables can be used to optimize hardware gener-ated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to prede-termine min/max ranges for variables to reduce the bitwidth re-quired to represent variables in hardware. Bitmask analysis char-acterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don’t-cares permit hard-ware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analy-sis in terms of their potential to impact area and speed of HLS-generated hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level optimizations in HLS based on static analysis reduce circuit area by 9%, on av-erage, while additional optimizations...
Abstract—We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi... more Abstract—We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core processors. In the coarse-grained approach, sets of design signals are assigned to different processor cores and routed concurrently. Communica-tion between cores is through the MPI (message passing interface) communications protocol. In the fine-grained approach, the task of routing an individual load pin on a signal is parallelized using threads. Specifically, as FPGA routing resources are traversed during maze expansion, delay calculation, costing and priority queue insertion for these resources execute concurrently. The proposed techniques provide deterministic/repeatable results. Moreover, the coarse and fine-grained approaches are not mutu-ally exclusive and can be used in tandem. Results show that on a 4-core processor, the techniques improve router run-time by ∼2.1×, on average, with no significant impact on circuit speed performance or interconnect resource usage. I.
Embedded system designers can achieve energy and performance benefits by using dedicated hardware... more Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, im-plementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelera-tor design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incremen-tally migrate portions of the program to hardware accelerators im-plemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodol-ogy and system architecture, and discusses ongoing work on pro-filing, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Abstract—In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augment... more Abstract—In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some onchip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles. I.
With the ever-increasing complexity of integrated circuits, the elimination of all design errors ... more With the ever-increasing complexity of integrated circuits, the elimination of all design errors before fabrication is becoming more difficult. This increases the need to find design errors in chips after fabrication. This task, termed post-silicon debug, can be made easier if it is possible to obtain a trace of states that leads to a known state. BackSpace, a proposal for a new debug infrastructure which provides such a trace has been recently presented. BackSpace combines formal analysis with on-chip instrumentation. In this thesis, we show that BackSpace can be made practical by modifying the architecture and debug flow to address the area overhead, and also by addressing on-chip realities such as non-determinism and signal propagation delay. Additionally, this thesis describes a proof-of-concept implementation of a complex processor instrumented with the debug architecture and shows that BackSpace can produce traces hundreds of cycles long. Our results indicate that the area overhead of the breakpoint circuit, a main component of the debug architecture, can be reduced to 5% for our prototype, while still allowing the debug flow to create state-accurate traces. was done independently, while some of it was done in collaboration with Flavio De Paula. The research for Chapters 2 and 3 was performed independently from Flavio's research. Flavio made several contributions to Chapter 4. He was responsible for the pre-image computation software running on the PC connected to the prototype. Additionally, he created a mailbox communication protocol that is used to enable communication between the PC and the FPGA prototype. Flavio wrote the code that uses the mailbox communication protocol on the PC side, but not on the prototype side. Although I was responsible for implementing the OpenRISC 1200 in hardware, Flavio eased the process by first successfully simulating its operation in software. Additionally, Flavio cross-compiled the code for the benchmarks which ran on the OpenRISC 1200. Two papers and two demonstrations have resulted from our work on BackSpace. The two papers both contain material written by Flavio de Paula, Dr.
2008 Formal Methods in Computer-Aided Design, 2008
IC technology continues to closely follow Moore's Law, while the ability to verify designs lags b... more IC technology continues to closely follow Moore's Law, while the ability to verify designs lags behind. The International Technology Roadmap for Semiconductors (ITRS) predicts production of chips using 16nm technology already by 2015, but the verification gap, i.e., advancements in verification technology not keeping up with advancements in design technology, seems to be also increasing at a fast pace. A recent study shows a drop of more than 10 percentage points in the number of 1 st-silicon success from 2002 through 2009. By 2007, more than two-thirds of chips had to be respun due to bugs. The increasing verification gap is to blame. Unfortunately, because more bugs are slipping into the fabricated chip, post-silicon debug is the only way to catch them. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. The focus of post-silicon debug is design errors, whereas traditional VLSI test focuses on random manufacturing defects on each fabricated chip. Post-silicon debug currently consumes more than half of the total verification schedule on typical large designs, and the problem is growing worse. The general problem of post-silicon debug is broad and multi-faceted, spurring a diverse variety of research. In this thesis, I focus on one of the most fundamental tasks: getting an execution trace of on-chip signals for many cycles leading up to an observed bug or crash. Until such a trace is obtained, further debugging is essentially impossible, as there is no way to know what happened on the chip. However, the ever-increasing chip complexity compounded with new features that add non-determinism makes computing accurate traces extremely difficult.
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based... more We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based logic blocks, multiplier/DSP blocks and block RAMs. Specifically, we adapt a state-of-the-art ASIC-based analytical placer to target FPGAs with heterogeneous blocks located at discrete locations throughout the fabric. Our placer also handles macros of LUT-based blocks with specific layout requirements, such as carry chains. Results show that our placer delivers a 4× speedup, on average, compared to Altera's non-timing driven flow, at the cost of a 5% increase in postrouted wirelength, and an 11× speedup compared to Altera's timing-driven flow, at the cost of a 4% increase in post-routed wirelength and a 9% reduction in maximum operating frequency. We also compare with an academic simulated annealing-based placer and demonstrate a 7.4× runtime advantage with 6% better placement quality.
2011 21st International Conference on Field Programmable Logic and Applications, 2011
We propose a new FPGA routing approach that, when combined with a low-cost architecture change, r... more We propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no increase in critical path delay. Our approach begins with traditional PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. Our approach points to a new research direction: reducing FPGA CAD run-time by exploring FPGA architectures and algorithms together.
2008 Ninth International Workshop on Microprocessor Test and Verification, 2008
In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with s... more In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some onchip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles.
2010 International Conference on Field-Programmable Technology, 2010
We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core pro... more We consider coarse and fine-grained techniques for parallel FPGA routing on modern multi-core processors. In the coarse-grained approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the MPI (message passing interface) communications protocol. In the fine-grained approach, the task of routing an individual load pin on a signal is parallelized using threads. Specifically, as FPGA routing resources are traversed during maze expansion, delay calculation, costing and priority queue insertion for these resources execute concurrently. The proposed techniques provide deterministic/repeatable results. Moreover, the coarse and fine-grained approaches are not mutually exclusive and can be used in tandem. Results show that on a 4-core processor, the techniques improve router run-time by ∼2.1×, on average, with no significant impact on circuit speed performance or interconnect resource usage.
2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013
Embedded system designers can achieve energy and performance benefits by using dedicated hardware... more Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source highlevel synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Formal-Analysis-Based Trace Computation for Post-Silicon Debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
Abstract This paper presents a post-silicon debug methodology that provides a means to rewind, or... more Abstract This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is ...
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We present parallelization and heuristic techniques to reduce the run-time of field-programmable ... more We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over $3\times$ speedup versus a sequential baseline. In our parallel approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the message passing interface communications protocol. We propose a
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Papers by Marcel Gort