Papers by Manuel Sanchez-Raya
Ingeniería Técnica Informática: Sistemas de Gestión, 3º curso "Redes
Portable Device for Information Sharing Between Mass Storage Devices
1. Portable device for exchanging data between mass storage devices comprising a microprocessor t... more 1. Portable device for exchanging data between mass storage devices comprising a microprocessor that in turn incorporates at least one central processing unit, a memory and a plurality of input and output units, a screen display data and a communication interface with the user, and a buffer SRAM connected to said microprocessor and characterized in that it comprises at least two USB ports connected to a multiplexer so that it is only active one at a time, and at least an input SD card type memory, all powered electrically by a bateria.2. Device according to claim 1 wherein said multiplexer inputs are connected to data pins of each USB connector.
Defending electronic systems against hardware attack
2016 Technologies Applied to Electronics Teaching (TAEE), 2016
Hardware attack is becoming an important scenario in the system design. Pupils who study design o... more Hardware attack is becoming an important scenario in the system design. Pupils who study design of electronic and computer systems must know this scenario and possible solutions against this kind of attacks. This work is a set of exercises to know some vulnerabilities in electronic and computer systems depending on the behavioral implementation. Two cases of study will be considered: timing analysis and differential fault analysis (DFA). The study of each attack will be divided into three stages: the use of the vulnerability as attack; the study of the vulnerability; and the elimination or reduction of it.
Sensors
For the monitoring of bone regeneration processes, the instrumentation of the fixation is an incr... more For the monitoring of bone regeneration processes, the instrumentation of the fixation is an increasingly common technique to indirectly measure the evolution of bone formation instead of ex vivo measurements or traditional in vivo techniques, such as X-ray or visual review. A versatile instrumented external fixator capable of adapting to multiple bone regeneration processes was designed, as well as a wireless acquisition system for the data collection. The design and implementation of the overall architecture of such a system is described in this work, including the hardware, firmware, and mechanical components. The measurements are conditioned and subsequently sent to a PC via wireless communication to be in vivo displayed and analyzed using a developed real-time monitoring application. Moreover, a model for the in vivo estimation of the bone callus stiffness from collected data was defined. This model was validated in vitro using elastic springs, reporting promising results with ...
Sensors, 2017
This paper presents a study about hardware attacking and clock signal vulnerability. It considers... more This paper presents a study about hardware attacking and clock signal vulnerability. It considers a particular type of attack on the clock signal in the I2C protocol, and proposes the design of a new sensor for detecting and defending against this type of perturbation. The analysis of the attack and the defense is validated by means of a configurable experimental platform that emulates a differential drive robot. A set of experimental results confirm the interest of the studied vulnerabilities and the efficiency of the proposed sensor in defending against this type of situation.
Defending electronic systems against hardware attack
2016 Technologies Applied to Electronics Teaching (TAEE), 2016
Hardware attack is becoming an important scenario in the system design. Pupils who study design o... more Hardware attack is becoming an important scenario in the system design. Pupils who study design of electronic and computer systems must know this scenario and possible solutions against this kind of attacks. This work is a set of exercises to know some vulnerabilities in electronic and computer systems depending on the behavioral implementation. Two cases of study will be considered: timing analysis and differential fault analysis (DFA). The study of each attack will be divided into three stages: the use of the vulnerability as attack; the study of the vulnerability; and the elimination or reduction of it.
Diseño de bloques analógicos de alta velocidad y técnicas de procesamiento digital para aplicación en detectores de física nuclear
Tradicionalmente, los sistemas front-end para detectores de particulas en aplicaciones de fisica ... more Tradicionalmente, los sistemas front-end para detectores de particulas en aplicaciones de fisica nuclear se han realizado mediante bloques analogicos discretos. La interconexion de los mismos dentro de la cadena de instrumentacion electronica permite extraer la informacion de interes, que en la mayoria de aplicaciones, son la energia de las particulas y el instante de llegada de las mismas. En otros casos, tambien resulta necesario identificar el tipo de particula que ha impactado en el sistema de deteccion. Las nuevas instalaciones de haces radiactivos que se van a construir en Europa en los dos proximas decadas constituyen un desafio para el desarrollo de una nueva generacion de sistemas de deteccion de particulas cuyos esfuerzos deben estar enfocados hacia los sensores semiconductores, la electronica de acondicionamiento y los sistemas de control. Esta tesis presenta un doble enfoque: por un lado, se centra en desarrollar bloques analogicos discretos claves en sistemas front-end que acondicionan las senales procedentes de detectores semiconductores, y que sean capaces de satisfacer los exigentes requisitos de velocidad, linealidad, resolucion y precision. Por otro lado, en el dominio digital se ha desarrollado una nueva tecnica para identificar particulas. En la tesis se propone un nuevo amplificador sensible a la carga que presenta la salida de carga convencional para medir la energia depositada por las particulas en el detector, y tambien una salida de corriente o temporizacion que mantiene la forma del pulso, y que se puede utilizar para la identificacion de particulas mejorando otros metodos convencionales basados en la medida del tiempo de subida de la senal de carga. El preamplificador ha sido disenado con reducidas dimensiones y bajo consumo de potencia. En segundo lugar se ha disenado un shaper unipolar casi-gausiano basado en la utilizacion de un filtro activo RC con polos complejos. El circuito presenta un nuevo esquema del circuito de restauracion de la linea de base de los pulsos, e incorpora un sistema de control remoto de sus principales parametros de funcionamiento para facilitar la realizacion de experimentos en tiempo real. Finalmente, dentro de la parte analogica de un sistema front-end, tambien se ha implementado un discriminador de fraccion constante adecuado para medir el tiempo de vuelo de las particulas que inciden en los detectores que alcanza elevadas resoluciones del orden de 500 ps para un amplio rango dinamico. Por otro lado, el desarrollo de las nuevas tecnologias hace atractivo la incorporacion de tecnicas de procesamiento digital en este campo de investigacion permitiendo una simplificacion de la electronica y un mayor grado de flexibilidad. En esta linea, se propone una nueva tecnica de identificacion de iones mediantes el analisis de la forma de los pulsos utilizando redes neuronales artificiales implementadas en una FPGA. El diseno de dicha red ha sido realizada mediante un modelo configurable VHDL para una mejor adaptacion a las caracteristicas de un experimento en particular. Los disenos de esta tesis estan orientados a detectores de silicio que son utilizados en sistemas de deteccion de particulas cargadas para aplicaciones de espectroscopia. Traditionally, front-end systems for particle detectors in nuclear physics applications were made with discrete analog blocks. The interconnecting of these blocks in the chain of electronic instrumentation allows extracting the relevant information, which in most applications, are the energy of the particles and the time of arrival. In other cases, also it is necessary to identify the type of particle which has impacted on the detection system. The new radioactive beam facilities that will be built in Europe in the next two decades are a challenge for the development of a new generation of particle detection systems and the efforts must be focused on semiconductor sensors, conditioning electronics and control systems. This thesis presents a dual approach: first, it focuses on developing discrete analog blocks for front-end systems that conditioning the signals from semiconductor detectors, and that they are able to meet the demanding requirements of speed, linearity, resolution and accuracy. Furthermore, in the digital domain has been developed a new technique for identifying of particles. The thesis proposes a new charged sensitive amplifier that exhibits the conventional charge output to measure the energy deposited by the particles on the detector, and also a current output or timing output that keeps the pulse shape, and can be used for identification of particles improving conventional methods relying on measuring the rise time of the charge signal. The preamplifier is designed with small size and low power consumption. Secondly we have designed a near-Gaussian unipolar shaper based on the use of an RC active filter with complex poles. The circuit presents a new base line restorer for the pulses and includes a remote…
Hardware Attacks on Mobile Robots: I2C Clock Attacking
Advances in Intelligent Systems and Computing, 2015
This paper presents a study on various types of attacks on the security of a robotic system. The ... more This paper presents a study on various types of attacks on the security of a robotic system. The work focuses on hardware attacks, and particularly considers vulnerable features of the I2C protocol. An analysis of the effects of these attacks, when they are applied on a differential driving mobile robot that aims to track a path, is presented. The paper shows how, with such actions, it is possible to modify the behavior of the robot without leaving traces of the attack and also maintaining the system without any damage.
Implementation of a neural network for digital pulse shape analysis on a FPGA for on-line identification of heavy ions
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2012
ABSTRACT Pulse shape analysis techniques for the identification of heavy ions produced in nuclear... more ABSTRACT Pulse shape analysis techniques for the identification of heavy ions produced in nuclear reactions have been recently proposed as an alternative to energy loss and time of flight methods. However this technique requires a large amount of memory for storing the shapes of charge and current signals. We have implemented a hardware solution for fast on-line processing of the signals producing the relevant information needed for particle identification. Since the pulse shape analysis can be formulated in terms of a pattern recognition problem, a neural network has been implemented in a FPGA device. The design concept has been tested using 12,13C ions produced in heavy ion reactions. The actual latency of the system is about 20 μs when using a clock frequency of 50 MHz.
FPGA-based implementation of a real-time timing measuring device
2013 European Conference on Circuit Theory and Design (ECCTD), 2013
ABSTRACT The design and implementation of a frequency meter that operates in real-time is present... more ABSTRACT The design and implementation of a frequency meter that operates in real-time is presented. It has been implemented in a low cost FPGA device, concretely, in a SPARTAN-3AN700. The measuring device is configurable in resolution time and in maximum measurable period. The main characteristics of the frequency meter are a minimum resolution time of 2.60 ns and a minimum measurable period of four times the resolution time.
ROS Methodology to Work with Non-ROS Mobile Robots: Experimental Uses in Mobile Robotics Teaching
Advances in Intelligent Systems and Computing, 2014
This paper presents a robotics platform for experimental and teaching purposes that allows contro... more This paper presents a robotics platform for experimental and teaching purposes that allows control and remote access by using plain sockets (regular TCP/IP sockets) and websockets respectively. The system has been built from ROS middleware (Robot Operating System) and is capable of controlling multiple user operations. The robot hardware connected to sensors or/and actuators does not support ROS due to its features. This article focus attention on describing a work methodology to establish communication of the non-ROS robotic platforms and ROS.
High speed low power FEE for silicon detectors in nuclear physics applications
ABSTRACT A high speed, low power and programmable readout front-end system is presented for silic... more ABSTRACT A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100 ns, 200 ns and 400 ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130 nm CMOS technology and powered from a 1.2 V supply. The output pulse has peak amplitude of 200 mV for an input energy of 5 MeV from the detector. A power consumption low noise tradeoff will be considered.
Low voltage analog readout channel based on gain-boosted amplifiers
ABSTRACT This paper presents a design of a single readout front-end channel for energy spectrosco... more ABSTRACT This paper presents a design of a single readout front-end channel for energy spectroscopy. The front-end electronic system comprises a charge sensitive amplifier and a pulse shaping amplifier. Novel techniques based on regulated cascode circuits to increase the gain are proposed. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. The analog system has been designed in a 90 nm technology and optimized to match a detector capacitance of 5 pF. Simulation results confirm the advantages of the proposed approaches in terms of gain, speed, linearity and power consumption.
VLSI Implementation of digital frequency sensors as hardware countermeasure
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012
ABSTRACT Non-invasive attacks are considered among the more serious threats for the hardware secu... more ABSTRACT Non-invasive attacks are considered among the more serious threats for the hardware security due to there not exist evidences of them. Among these attacks, the clock glitch attack is one of the easier implementations. The typical countermeasure in front of this attack is a frequency sensor. In this paper, a VLSI design of a frequency digital sensor is presented. The simulation results, in a 0.35um standard CMOS technology, show a minimum timing resolution of 1.91ns and a minimum allowed period of 6.8ns. Finally, this implementation has been compared with an analog solution. The digital solution improves to the analog solution in timing resolution, power consumption, area consumption and propagation delay.
Lecture Notes in Computer Science, 2005
In this work, the optimization of circuits design by using multiobjective evolutionary algorithm ... more In this work, the optimization of circuits design by using multiobjective evolutionary algorithm is addressed. This methodology enable to deal with circuit specifications-formulated as objective functions-that can be conflicting and want to be optimize at the same time. After the optimization process, a set of different trade-off solutions for the design of the circuit is obtained. This way, SPEA (Strength Pareto Evolutionary Algorithm) has been tested as optimizer of an hybrid CBL/CMOS configurable cell. As a result, some conclusions about the optimized values of the transistor sizes of this cell in order to minimized some power comsumption and delay timing specifications are obtained.
VLSI Circuits and Systems II, 2005
Optimization of Master-Slave Flip-Flops for High-Performance Applications
Integrated Circuit and …, 2006
The design of high-performance master-slave flip-flops is of crucial importance in modern VLSI. T... more The design of high-performance master-slave flip-flops is of crucial importance in modern VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization ...
Low power low noise high speed tunable CMOS radiation detection system
ABSTRACT This paper presents a design of low power and low noise, high speed readout front-end sy... more ABSTRACT This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC.
A 1.2-V 450- <formula> <tex> \(\boldsymbol \mu \) </tex> </formula> W <formula> <tex> \(\boldsymbol G_{{\boldsymbol m}}\) </tex> </formula> - <formula> <tex> \(\boldsymbol C\) </tex> </formula> Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
ABSTRACT A third-order Gm-C Chebyshev low-pass filter based on a novel gain-boosted tunable trans... more ABSTRACT A third-order Gm-C Chebyshev low-pass filter based on a novel gain-boosted tunable transconductor is presented. The transconductor employs local negative feedback for linearization controlling the drain voltage of the input transistors biased in the triode region. The gain boosted feedback amplifier is based on quasi-floating gate MOS transistors and its adjustable biasing current allows tuning the cutoff frequency of the filter. The filter is intended to be used in the baseband section of a zero-IF bluetooth low energy receiver and it has been fabricated in a standard 0.13-μm CMOS technology with a nominal cutoff frequency of 500 kHz. The power consumption of the overall filter is 450 μW with a supply voltage of 1.2 V. The measurement results show a third-order intermodulation distortion of -46.4 dB for two input tones located at the passband of the filter. The filter occupies a silicon area of 0.08 mm2.
Linear Tunable Analog Front-End Electronics for Silicon Charged-Particle Detectors
IEEE Transactions on Instrumentation and Measurement, 2015
ABSTRACT A linear front-end electronic system based on a high-speed charge sensitive amplifier an... more ABSTRACT A linear front-end electronic system based on a high-speed charge sensitive amplifier and a tunable shaping amplifier suitable for silicon detectors has been presented. The designed charge sensitive amplifier features simplicity and compactness. It is based on the combination of a low-noise field-effect transistor input device and a current feedback opamp ensuring high frequency and small rise time. The circuit provides both an energy signal and a timing signal. The shaping amplifier is a fifth-order complex filter based on an opamp-RC topology providing a nearly Gaussian response. The shaper also includes a pole-zero cancellation circuit and a base line restorer to preclude the pileup of subsequent input signals. A control system has been developed to adjust the main parameters of the channel. The designed readout channel has been optimized for a medium energy range up to 50 MeV coupled to silicon detectors up to 100 pF. Its feasibility for nuclear physics applications has been experimentally validated.
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Papers by Manuel Sanchez-Raya